Sharp UP-3300 (serv.man16) Service Manual ▷ View online
3) Terminal Name and Description (MB62H149)
Fig. 7
Pin
No.
Terminal
name
Host/
Sub
In/
Out
Description
1
CLK
Sub
In
Clock in (16 MHz)
2
—
—
—
N.U.
3
IORQ
Sub
In
I/O request
4
MREQ
Sub
In
Memory request
5
RDS
Sub
In
Read from sub
6
WRS
Sub
In
Write from sub
7
INTS
Sub
Out
Interrupt to sub
8
φ
Sub
Out
Clock out
9
TM0
Sub
In
Timer 0
10
TM1
Sub
Out
Timer 1
11
MRD
Sub
Out
Memory read
12
VSS
—
—
GND
13
WAIT
Sub
Out
Wait signal
14
A15
Sub
Out
Address bus for DMA
16
A9
Sub
Out
17
A8
Sub
Out
18
A5
Sub
In
19
A4
Sub
In
20
A1
Sub
In
21
A0
Sub
In
22
DAK01
Sub
In
DMA acknowledge 0+1
23
—
—
—
N.U.
24
MWR0
Sub
Out
Memory write
25
D7
Sub
I/O
Data bus
26
D6
Sub
I/O
27
D5
Sub
I/O
28
D4
Sub
I/O
29
D3
Sub
I/O
30
D2
Sub
I/O
31
D1
Sub
I/O
32
D0
Sub
I/O
33
VDD
—
—
+5V
34
—
—
—
N.U.
35
RES
Host
In
Reset
Pin
No.
Terminal
name
Host/
Sub
In/
Out
Description
36
IO/WR
Sub
I/O
I/O write
37
IO/RD
Sub
I/O
I/O read
38
AEN
Sub
In
Address enable from DMAC
39
AST
Sub
In
Address strobe from DMAC
40
TCS
Sub
In
Terminal count
41
DAK23
Sub
In
DMA acknowledge 2+3
42
DRQRS
Sub
Out
DMA request read to sub
43
DRQWS
Sub
Out
DMA request write to sub
44
RDH
Host
In
Read from Host
45
WRH
Host
In
write from Host
46
INTH
Host
Out
Interrupt to host
47
DAK
Host
In
DMA acknowledge from host
48
TCH
Host
In
Terminal count from host
49
DRQWH
Host
Out
DMA request read to host
50
DRQWH
Host
Out
DMA request write to host
51
CS
Host
In
Chip select from host
52
VSS
—
—
GND
53
—
—
—
N.U.
54
DB0
Host
I/O
Data bus
55
DB1
Host
I/O
Data bus
56
DB2
Host
I/O
Data bus
57
DB3
Host
I/O
Data bus
58
DB4
Host
I/O
Data bus
59
DB5
Host
I/O
Data bus
60
DB6
Host
I/O
Data bus
61
DB7
Host
I/O
Data bus
62
AB0
Host
In
Address bus from host
63
—
—
—
N.U.
64
AB1
Host
In
Address bus from host
65
COL
Sub
In
Collision detect signal
66
RDI
Sub
In
Receive data from receiver
67
TDI
Sub
Out
Transmmit data to driver
68
RTS
Sub
In
Request to send
69
RXC
Sub
Out
Receive clock to ADLC
70
RXD
Sub
Out
Receive data to ADLC
71
TXC
Sub
Out
Transmmit clock
72
TXD
Sub
In
Transmmit data
73
VDD
—
—
+5V
74
E
Sub
In
Enable clock to ADLC
75
IRQ
Sub
In
Interrupt request from ADLC
76
LCS
Sub
Out
Link controller chip select
77
—
—
—
N.U.
78
RS1
Sub
Out
Register select 1
79
RS0
Sub
Out
Register select 0
80
MSK
Sub
Out
Mask signal
14
17.
9
±
0.
4
20
23.9 ±
0. 6
0.8 ±
0.15
0.35 ±
0.1
INDEX
LEAD
NO
1
24
25
40
41
64
65
80
7 – 17
2-8. VGA controller (MN89303A)
1) Pin Configuration
2) Block diagram
1
XIN
2
GND
3
AEN
4
/SBEH
5
/IOWR
6
/IORD
7
/SMEMW
8
/SMEMR
9
A21
10
A20
11
SA19
12
13
13
SA17
14
SA16
15
SA15
16
SA14
17
SA13
18
SA12
19
SA11
20
SA10
21
SA9
22
SA8
23
SA7
24
SA6
25
SA5
26
SA4
27
SA3
28
SA2
29
SA1
30
SA0
31
32
32
12
8
XO
12
7
12
6
MINTEST
12
5
TEST
12
4
RESET
12
3
VDD
12
2
GND
12
1
MD0
12
0
MD1
11
9
MD2
11
8
MD3
11
7
MD4
11
6
MD5
11
5
MD6
11
4
MD7
11
3
MD8
11
2
MD9
11
1
VDD
11
0
GND
10
9
MD10
10
8
MD11
10
7
MD12
10
6
MD13
10
5
MD14
10
4
MD15
10
3
/WE
10
2
/LCAS
10
1
/UCAS
10
0
/RAS
99
VDD
98
GND
97
MA
0
33
GND
34
VDD
35
SD15
36
SD14
37
SD13
38
SD12
39
GND
40
SD11
41
SD10
42
SD9
43
VDD
44
SD8
45
SD7
46
SD6
47
GND
48
SD5
49
SD4
50
SD3
51
SD2
52
SD1
53
SD0
54
GND
55
VDD
56
IOC
HRDY
57
/MEMCS16
58
/IOCS16
59
GND
60
VDD
61
DCLK
62
DISP
63
LP
64
FP
GND
SA18
/BIOSEN
/REFRESH
96
MA1
95
MA2
94
MA3
93
MA4
92
MA5
91
MA6
90
MA7
89
MA8
88
MA9
87
VDD
86
GND
85
84
84
LCDON
83
BACKON
82
LD0
81
LD1
80
LD2
79
LD3
78
LD4
77
LD5
76
LD6
75
LD7
74
VDD
73
GND
72
UD0
71
UD1
70
UD2
69
UD3
68
UD4
67
UD5
66
65
65
LOGICON
UD6
UD7
UD7
1
XIN
RESET
TEST/MINTEST
124
126/125
ADDRESS[21:0]
3
LCD panel
controller
UD[7:0]
LD[7:0]
BACKON
LCDON
83
FO
DISP
DCLK
LOGICON
84
85
63
64
62
LP
61
SD[15:0]
AEN
SBHE
IOWR
IORD
SMEMW
SMEMR
IOCHRDY
REFRESH
MEMCS16
IOCS16
4
5
6
7
8
56
32
57
58
Host
interface
LCD/CRT
controller
Gray scale
engine
Memory
write
buffer
RAM table
Hardware
cursor
Attributer
Video FIFO
Mmory
interface
Access
attributer
Guraphics
controller
MA[9:0]
MD[15:0]
RAS
UCAS
LCAS
WE
BIOSEN
100
101
102
103
31
7 – 18
3) Pin configuration
Pin
No.
Symbol
Signal
name
In/
Out
Function
1
XIN
XIN
In
25.175MHz
2
GND
GND
In
GND
3
AEN
GND
In
GND
4
/SBEH
/SBEH
In
System byte high enable
5
/IOWR
/IOWR
In
I/O write
6
/IORD
/IORD
In
I/O read
7
/SMEMW
/SMEMW
In
Meory write
8
/SMEMR
/SMEMR
In
Memory read
9
A21
GND
In
GND
10
A20
GND
In
GND
11
SA19
VCC
In
+5V
12
SA18
GND
In
GND
13
SA17
VCC
In
+5V
14
SA16
A16
In
Address bus
15
SA15
A15
In
Address bus
16
SA14
A14
In
Address bus
17
SA13
A13
In
Address bus
18
SA12
A12
In
Address bus
19
SA11
A11
In
Address bus
20
SA10
A10
In
Address bus
21
SA9
A9
In
Address bus
22
SA8
A8
In
Address bus
23
SA7
A7
In
Address bus
24
SA6
A6
In
Address bus
25
SA5
A5
In
Address bus
26
SA4
A4
In
Address bus
27
SA3
A3
In
Address bus
28
SA2
A2
In
Address bus
29
SA1
A1
In
Address bus
30
SA0
A0
In
Address bus
31
/BIOSEN
NC
In
NC
32
/REFRESH
/RFSH
In
Refresh signal
33
GND
GND
In
GND
34
VDD
VCC
In
+5V
35
SD15
D7
I/O
Data bus
36
SD14
D6
I/O
Data bus
37
SD13
D5
I/O
Data bus
38
SD12
D4
I/O
Data bus
39
GND
GND
In
GND
40
SD11
D3
I/O
Data bus
41
SD10
D2
I/O
Data bus
42
SD9
D1
I/O
Data bus
43
VDD
VCC
In
+5V
44
SD8
D0
I/O
Data bus
45
SD7
D15
I/O
Data bus
46
SD6
D14
I/O
Data bus
47
GND
GND
In
GND
48
SD5
D13
I/O
Data bus
49
SD4
D12
I/O
Data bus
50
SD3
D11
I/O
Data bus
51
SD2
D10
I/O
Data bus
52
SD1
D9
I/O
Data bus
53
SD0
D8
I/O
Data bus
54
GND
GND
In
GND
55
VDD
VCC
In
+5V
56
IOCHRDY
/VWAITI
Out
Channel ready signal
57 /MEMCS16
NC
In
NC
58
/IOCS16
NC
In
NC
59
GND
GND
In
GND
Pin
No.
Symbol
Signal
name
In/
Out
Function
60
VDD
VCC
In
+5V
61
DCLK
XCK
Out
Data shift clock
62
DISP
DISP
Out
Display enable
63
LP
LP
Out
Line pulse
64
FP
YD
OUt Frame pulse
65
UD7
DU7
Out
Upper data
66
UD6
DU6
Out
Upper data
67
UD5
DU5
Out
Upper data
68
UD4
DU4
Out
Upper data
69
UD3
DU3
Out
Upper data
70
UD2
DU2
Out
Upper data
71
UD1
DU1
Out
Upper data
72
UD0
DU0
Out
Upper data
73
GND
GND
In
GND
74
VDD
VCC
In
+5V
75
LD7
DL7
Out
Lower data
76
LD6
DL6
Out
Lower data
77
LD5
DL5
Out
Lower data
78
LD4
DL4
Out
Lower data
79
LD3
DL3
Out
Lower data
80
LD2
DL2
Out
Lower data
81
LD1
DL1
Out
Lower data
82
LD0
DL0
Out
Lower data
83
BACKON
BKLT
Out
Back light On
84
LCDON
LCDON
Out
LCD drive power on signal
85
LOGICON
NC
Out
LCD logic power on signal
86
GND
GND
In
GND
87
VDD
VCC
In
+5V
88
MA9
NC
Out
NC
89
MA8
MA8
Out
Memory address bus
90
MA7
MA7
Out
Memory address bus
91
MA6
MA6
Out
Memory address bus
92
MA5
MA5
Out
Memory address bus
93
MA4
MA4
Out
Memory address bus
92
MA3
MA3
Out
Memory address bus
91
MA2
MA2
Out
Memory address bus
92
MA5
MA5
Out
Memory address bus
93
MA4
MA4
Out
Memory address bus
94
MA3
MA3
Out
Memory address bus
95
MA2
MA2
Out
Memory address bus
96
MA1
MA1
Out
Memory address bus
97
MA0
MA0
Out
Memory address bus
98
GND
GND
In
GND
99
VDD
VCC
In
VCC
100
/RAS
/RASV
Out
RAS address strobe
101
/UCAS
/UCASV
Out
Upper CAS address strobe
102
/LCAS
/LCASV
Out
Lower CAS address strobe
103
/WE
/WEV
Out
Write enable
104
MD15
MD15
I/O
Memory data
105
MD14
MD14
I/O
Memory data
106
MD13
MD13
I/O
Memory data
107
MD12
MD12
I/O
Memory data
108
MD11
MD11
I/O
Memory data
109
MD10
MD10
I/O
Memory data
110
GND
GND
In
GND
111
VDD
VCC
In
+5V
112
MD9
MD9
I/O
Memory data
113
MD8
MD8
I/O
Memory data
114
MD7
MD7
I/O
Memory data
7 – 19
Pin
No.
Symbol
Signal
name
In/
Out
Function
115
MD6
MD6
I/O
Memory data
116
MD5
MD5
I/O
Memory data
117
MD4
MD4
I/O
Memory data
118
MD3
MD3
I/O
Memory data
119
MD2
MD2
I/O
Memory data
120
MD1
MD1
I/O
Memory data
121
MD0
MD0
I/O
Memory data
122
GND
GND
In
GND
123
VDD
VCC
In
+5V
124
RESET
RESET
In
Reset signal
125
MINTEST
GND
In
GND
126
TEST
GND
In
GND
127
GND
GND
In
GND
128
XO
XO
Out
25.175MHz
2-9. CKDC9 (HD404728A91FS)
1) General description
The CKDC7 is a 4-bit microcomputer developed for the UP-3300 and
provides functions to control the real-time clock, keys, and displays.
The basic functions of the CKDC7 are shown below.
provides functions to control the real-time clock, keys, and displays.
The basic functions of the CKDC7 are shown below.
Keys:
The CKDC9 is capable of controlling a maximum of 256
momentary keys. (Sharp 2-key rollover control)
Simultaneous scanning of key and switch
(When a key is scanned, the state of a mode and clerk
switch is also buffered. The host can scan the state of
switch together with the key entry data at the same time
the key is scanned.)
momentary keys. (Sharp 2-key rollover control)
Simultaneous scanning of key and switch
(When a key is scanned, the state of a mode and clerk
switch is also buffered. The host can scan the state of
switch together with the key entry data at the same time
the key is scanned.)
Switches:
Mode switch with 14 positions maximum
8-bit clerk (cashier) switch
2-bit feed switch
1-bit receipt on/off switch
1-bit option switch
4-bit general-purpose switch (1-bit is used for keyboard
select)
8-bit clerk (cashier) switch
2-bit feed switch
1-bit receipt on/off switch
1-bit option switch
4-bit general-purpose switch (1-bit is used for keyboard
select)
Displays:
16-column dot display
12-column 7-segment display (column digit selectable)
All column blink controlled for the dot and 7-segment
display decimal point and indicators
Programmable patterns for 7-segment display:
Four patterns
Internal driver for 7-segment display
12-column 7-segment display (column digit selectable)
All column blink controlled for the dot and 7-segment
display decimal point and indicators
Programmable patterns for 7-segment display:
Four patterns
Internal driver for 7-segment display
Buzzer:
Single tone control
Clock:
Year, month, day of month, day of week, hour, minute
Alarm:
Hour, minute
Interrupt request (event control):
Detection of key input, switch position change, alarm
issue, and counter overflow
issue, and counter overflow
2) Pin description
Pin
No.
Symbol
Signal
name
In/
Out
Function
1
SB
SB
Out
Segment B
2
SC
SC
Out
Segment C
3
SD
SD
Out
Segment D
4
SE
SE
Out
Segment E
5
SF
SF
Out
Segment F
6
SG
SG
Out
Segment G
7
P4
AP
Out
8
P0
NC
—
NC
9
P1
NC
—
NC
10
P2
DP
Out
Decimal point
11
P3
ID
Out
Indicator
Pin
No.
Symbol
Signal
name
In/
Out
Function
12
MODR
VCC
—
+5V
13
CFSR
CFSR
In
Clerk key, Feed key, Switch return
signal
signal
14
KEX0
NC
Out
NC
15
KEX1
NC
Out
NC
16
RQ
GND
—
GND
17
SKR0
VCC
—
+5V
18
ST0
ST0
Out
Key strobe signal
19
ST1
ST1
Out
Key strobe signal
20
ST2
ST2
Out
Key strobe signal
21
ST3
ST3
Out
Key strobe signal
22
POFF
POFF
In
Power off signal
23
STOP
STOP
In
STOP signal
24
DDIG
VCC
—
+5V
25
DCS
DCS
—
Dot display controller chip select
DCS
DCS
26
VCC
VCKDC
—
+5V
27
SCK
SCK
In
Clock signal
28
HTS
HTS
In
Key data from host
29
STH
STH
Out
Key data to host
30
SDISP
GND
—
GND
31
BUZZ
BUZZ
Out
Buzzer
32
DSCK
DSCK
—
Dot display controller SCK
33
SRES
RESET
Out
Reset signal
34
DS0
DSO
—
Dot display controller SO
35
SHEN
SHEN
Out
Shift enable signal
36
IRQ
KRQ
Out
Key request signal
37
KR0
KR0
In
Key return signal
38
KR1
KR1
In
Key return signal
39
KR2
KR2
In
Key return signal
40
KR3
KR3
In
Key return signal
41
RESET
CKDCR
In
CKDC reset signal
42
OSC2
OSC2
—
Clock
43
OSC1
OSC1
—
Clock
44
GND
GND
—
GND
45
CL1
CL1
—
Time clock
46
CL2
CL2
—
Time clock
47
TEST
VCKDC
—
+5V
48
G0
G1
Out
Display digit signal
49
G1
G2
Out
Display digit signal
50
G2
G3
Out
Display digit signal
51
G3
G4
Out
Display digit signal
52
G4
G5
Out
Display digit signal
53
G5
G6
Out
Display digit signal
54
G6
G7
Out
Display digit signal
55
G7
G8
Out
Display digit signal
56
G8
G9
Out
Display digit signal
57
G9
G10
Out
Display digit signal
58
G10
G11
Out
Display digit signal
59
G11
NC
Out
NC
60
PO0
NC
NC
61
PO1
NC
NC
62
PO2
NC
—
NC
63
PO3
NC
—
NC
64
SA
SA
—
Segment A
7 – 20
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