Sharp ER-A850 (serv.man5) Service Manual ▷ View online
2-2-4. Segment control
CKDC4 directly drives the 7-segment display unit.
7 segment drive time chart
The display tube employs a grid blanking dynamic drive and operates
in the following timing.
7 segment drive time chart
The display tube employs a grid blanking dynamic drive and operates
in the following timing.
<7-segment display>
2-2-5. Data test
Host ECR
→
CKDC4 in the ER-A8DP PWB
1) Host ECR
→
ER-A8DP (loopback test)
1
Set the data "A" in the shift register of the host ECR.
2
Send the data "A" to the ER-A8DP with shift clock added to the
host ECR and read the data on the ER-A8DP.
host ECR and read the data on the ER-A8DP.
3
Set the data "B" to the host ECR.
4
Send the data "B" to the ER-A8DP with shift clock’s added by the
host ECR. Then, sen the previous data "A" in the ER-A8DP to the
host ECR.
host ECR. Then, sen the previous data "A" in the ER-A8DP to the
host ECR.
The host cash register transfers data to ER-A8DP after eigth shift
clocks. In this event, the contents of the ER-A8DP shift register
(data A) is not destroyed.
clocks. In this event, the contents of the ER-A8DP shift register
(data A) is not destroyed.
5
The host ECR checks if the returned data "A" are properly trans-
mitted. The data "B" returns to the host ECR to be checked after a
next data or a dummy data are sent.
mitted. The data "B" returns to the host ECR to be checked after a
next data or a dummy data are sent.
2) CKDC4
→
host (repeated transmission of the same
data twice)
1
Set the data "A" in the CKDC4 side shift register.
2
Sent the data "A" on the shift clock and read it on the host side.
3
Set the dame data "A" in the CKDC4 side shift register.
4
Again, sent the data "A" on the shift clock.
5
On the host side, compare the data "A" read in
2
to check if the
transmission was achieved properly.
2-2-6. ER-35DP operation check
The SHEN signal is used to check lock up of the ER-A8DP. Normally,
it will complete within 2msec before SHEN is set after the host ECR
completed data transmission. If SHEN was not received within the
predetermined time, it will be error processed as an error.
it will complete within 2msec before SHEN is set after the host ECR
completed data transmission. If SHEN was not received within the
predetermined time, it will be error processed as an error.
OKDC4
+5V
G0-G6
SA-SG, DP, ID
-29V
7SEG-display
-29V
36.2µ S
44.8µ S
45.8µ S
58.2µ S
778µ S
778µ S x 11
Gm
DP, ID
SA, SB, SC, SD
SE, SF, SG, AP
Gm+1
Host ECR
Shift register
CKDC4
ER-A8DP
SCK
OUT
IN
OUT
IN
HTS
STH
SCK
ECR
A
ER-A8P
Unpredicatable
ECR
ER-A8DP
A
B
ECR
ER-A8DP
A
B
ECR
ER-A8DP
A
B
A
A
Unpredicatable
Host
CKDC4
A
Host
CKDC4
A
Host
CKDC4
Host
A
CKDC4
SHEN
SCK
30µ s ~ 2mms
4
3. E
R
-A
8
D
P
C
ir
c
u
it d
iagr
a
m
F
1
A P
3
F
4
G
5
7 G
6
E
8
D
9
6 G
1 0
T R
1 2
5 G
1 4
4 G
1 8
C O M
2 0
D P
2 1
3 G
2 2
C
2 4
1 / 2
2 5
2 G
2 6
, G
2 8
B
2 9
1 G
3 0
A
3 1
F
3 3
DP
1
F
IP7
B1
3
88
8
8
8
88
8
G 1 1
G 1 0
G 9
G 8
S A
G 7
G 6
G 5
G 4
-2
9V
-2
9V
X4
R1
2
7
R1
2
9
R1
2
4
R
114
R
115
R
116
R1
1
8
X8
R
117
100
K
R
133
R
130
100
K
-29V
R
139
100K
-29V
D P
S C
G 2
C O M
1 / 2
S B
G 1
S A
G 0
G 0
S G
V F 1
S G
R1
2
3
0
A P
S F
S E
S D
G 6
I D
G 5
G 4
G 3
V F 2
S G
R
121
0
R
131
0
C O M / A P
12V
VC
C
R1
1
2
1.
5K
R1
1
9
5.
6K
6
5
7
8
9
1
2
T1
F1
15
0m
A
SB
SC
SD
SE
SF
ZD
1
R
D
3
6E
B3
C4
22
u
/63
V
R
137
R
122
R
125
R
126
R
134
R
136
R
120
R
132
R1
2
8
1
00K
X9
SB
1
SC
2
SD
3
SE
4
SF
5
SG
6
P4
7
P0
8
P1
9
P2
10
P3
11
MO
DR
12
CF
S
R
13
KE
X0
14
KE
X1
15
RQ
16
SKR
0
17
ST
0
18
ST
1
19
S T 2
2 0
S T 3
2 1
P O F F
2 2
S T O P
2 3
D D I G
2 4
D C S
2 5
V C C
2 6
S C K
2 7
H T S
2 8
S T H
2 9
S D I S P
3 0
B U Z Z
3 1
D S C K
3 2
SR
ES
33
DS
0
34
SH
EN
35
IR
Q
36
KR
0
37
KR
1
38
KR
2
39
KR
3
40
R
ESE
T
41
OS
C
2
42
OS
C
1
43
GN
D
44
CL
1
45
CL
2
46
TE
S
T
47
G0
48
G1
49
G2
50
G3
51
G 4
5 2
G 5
5 3
G 6
5 4
G 7
5 5
G 8
5 6
G 9
5 7
G 1 0
5 8
G 1 1
5 9
P O 0
6 0
P O 1
6 1
P O 2
6 2
P O 3
6 3
S A
6 4
IC
101
CK
DC4
G0
G1
G2
G3
R1
3
8
R
135
VC
C
X2
32.
768
KH
z
C
105
15p
R
106
1M
X1
4.
91
M
H
z
C
104
15p
VC
C
VC
C
PJ
1
PJ
SG
CO
M
/A
P
DP
ID
VF
1
VF
2
-29V
VC
C
Q1
C
3
144
D1
1S
S
8
2
R1
0
5
1.
5K
ZD
2
RD6
.8
E
B
2
VC
C
VC
C
R
103
4.
3
K
C1
0
3
0.
1
u
7
6
1
3
1 2
IC
1
A
IR
2339N
VC
C
VC
C
R1
1
0
10
K
R1
1
1
51
K
9
8
14
3
1 2
IC
1
C
IR
2339
N
R1
0
9
10K
C1
0
1
330p
R1
0
4
1
00K
VC
C
VC
C
R
108
1.
1
K
R
102
6.
2
K
5
4
2
3
1 2
IC1
B
IR
2
339N
R1
0
7
2.
2K
F
R1
1
W
/0
.3
9
1
2
3
4
5
6
7
8
9
10
CN1
VC
C
12
V
SH
EN
-
HT
S
ST
H
KR
ES
FB
5
FB
4
FB
3
FB
2
FB
1
VC
C
C1
0
2
0.
1u
C
110
470p
C
109
10
00p
C
108
470p
C1
0
7
4
70p
C
106
470p
OD
S
-
SC
K
-
C1
1
1
0.
1u
C3
10
u
/16
V
C2
1
0u/
10V
OS
VC
C
C1
0.
0
15u
11
10
13
3
1 2
IC1
D
IR
23
39N
VC
C
R
101
2.
4
K
F
R1
1
3
30K
F
8
7
6
5
4
3
2
1
A
B
C
D
1
2
3
4
5
6
7
8
D
C
B
A
5
4. PWB layout
6
4. PWB layout
6
Display
