Sharp ER-A770 (serv.man7) Service Manual ▷ View online
2-2-5. Data test
Host
CKDC9 in the UP-I16DP PWB
1) Host
UP-I16DP (loopback test)
Set the data "A" in the shift register of the host POS.
Send the data "A" to the UP-I16DP with shift clock added to the
HOST and read the data on the UP-I16DP.
HOST and read the data on the UP-I16DP.
Set the data "B" to the HOST.
Send the data "B" to the UP-I16DP with shift clock’s added by the
HOST. Then, sen the previous data "A" in the UP-I16DP to the
HOST.
HOST. Then, sen the previous data "A" in the UP-I16DP to the
HOST.
The host cash register transfers data to UP-I16DP after eigth shift
clocks. In this event, the contents of the UP-I16DP shift register
(data A) is not destroyed.
clocks. In this event, the contents of the UP-I16DP shift register
(data A) is not destroyed.
The HOST checks if the returned data "A" are properly transmit-
ted. The data "B" returns to the HOST to be checked after a next
data or a dummy data are sent.
ted. The data "B" returns to the HOST to be checked after a next
data or a dummy data are sent.
2) CKDC9
host (repeated transmission of the same
data twice)
Set the data "A" in the CKDC9 side shift register.
Sent the data "A" on the shift clock and read it on the host side.
Set the dame data "A" in the CKDC9 side shift register.
Again, sent the data "A" on the shift clock.
On the host side, compare the data "A" read in
to check if the
transmission was achieved properly.
2-2-6. UP-I16DP operation check
The /SHEN2A signal is used to check lock up of the UP-I16DP.
Normally, it will complete within 2msec before /SHEN2A is set after
the HOST completed data transmission. If /SHEN2A was not received
within the predetermined time, it will be error processed as an error.
Normally, it will complete within 2msec before /SHEN2A is set after
the HOST completed data transmission. If /SHEN2A was not received
within the predetermined time, it will be error processed as an error.
CKDC9
OUT
IN
OUT
IN
HTS2A
STH2A
/SCK2A
Host
Shift register
UP-I16DP
HOST
UP-I16DP
A
Unpredicatable
HOST
UP-I16DP
A
HOST
UP-I16DP
A
B
HOST
UP-I16DP
A
A
B
B
HOST
A
Unpredicatable
CKDC9
A
HOST
CKDC9
A
HOST
CKDC9
A
HOST
CKDC9
/SHEN2A
/SCK2A
30µs ~ 2ms
S
F
S
G
S
E
S
C
S
D
A
P
D
P
S
1
/
2
S
1
/
2
V
F
2
V
F
2
V
F
2
N
P
N
P
N
P
N
P
VF
2
S
A
S
B
G
1
1
G
1
0
G
9
G
8
G
7
G
6
G
5
G
4
G
3
G
2
G
1
D
1
9
D
1
8
D
1
7
D
1
6
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
G
5
D
G
6
D
G
7
D
G
8
D
G
9
D
G
1
0
D
G
1
1
D
G
1
2
D
G
1
3
D
G
1
4
D
G
1
5
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
G
5
D
3
1
D
3
2
D
3
3
D
3
4
D
2
9
D
2
8
D
2
7
D
2
6
D
2
5
D
2
4
D
2
3
D
2
2
D
2
1
D
2
0
V
F
1
D
G
0
D
G
1
D
G
2
D
G
3
D
G
4
G
6
G
7
G
8
G
9
G
1
0
G
1
1
D
3
0
V
F
1
V
F
1
2
1
1
3
4
56789
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 2
3 3
3 4
3 5
3 6
3 7
3 8
3 9
4 0
4 1
4 2
4 3
4 4
4 5
4 6
4 7
4 8
4 9
5 0
5 1
5 2
5 3
5 4
5 5
5 6
5 7
5 8
5 9
6 0
6 1
6 2
6 3
6 4
6 5
6 6
6 7
6 8
6 9
7 0
7 1
7 2
7 3
7 4
7 5
7 6
7 7
7 8
7 9
8 0
8 1
8 2
8 3
8 4
8 5
8 6
8 7
8 8
8 9
9 0
9 1
9 2
DI
SP
LA
Y T
U
B
E
11
2-
LT-
0
4
G
K
N
P
N
P
N
P
N
P
N
C
N
C
N
C
N
C
N
C
VF
1
R2
R3
R4
R5
R6
R7
R8
R9
SA
-2
6V
R1
10
0K
X
9
R25
R26
R27
10
0K
X
7
R28
10
0K
-2
6V
-2
6V
SB
1
SC
2
SD
3
SE
4
SF
5
SG
6
P4
7
P0
8
P1
9
P2
10
P3
11
MODR
12
CFSR
13
KE
X0
14
KE
X1
15
RQ
16
SK
R0
17
ST
0
18
ST
1
19
S T 2
2 0
S T 3
2 1
P O F F
2 2
S T O P
2 3
D D I G
2 4
D C S
2 5
V C C
2 6
S C K
2 7
H T S
2 8
S T H
2 9
S D I S P
3 0
B U Z Z
3 1
D S C K
3 2
SRE
S
33
DS0
34
SHE
N
35
IRQ
36
KR0
37
KR1
38
KR2
39
KR3
40
RESET
41
OS
C2
42
OS
C1
43
GN
D
44
CL1
45
CL2
46
TE
ST
47
G0
48
G1
49
G2
50
G3
51
G 4
5 2
G 5
5 3
G 6
5 4
G 7
5 5
G 8
5 6
G 9
5 7
G 1 0
5 8
G 1 1
5 9
P O 0
6 0
P O 1
6 1
P O 2
6 2
P O 3
6 3
S A
6 4
IC2
CKDC4
R23
R22
R21
R24
10
0K
X
4
R13
R14
R15
R16
R32
2K
X
7
R33
R34
R17
R19
R18
R20
G1
G2
G3
G4
-2
6V
DG
1
1
DG
1
0
DG
9
DG
8
DG
7
DG
6
DG
5
DG
4
DG
3
DG
2
DG
1
DG
0
VCC
R36
R37
R38
R35
2K
X
4
/RE
S
C27
47
0p
F
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
49
49
64
64
63
63
62
62
61
61
VCC2
60
60
59
59
58
58
57
57
56
56
55
55
54
54
53
53
52
52
51
51
50
50
10
10
11
11
12
12
1
3
/R
ES
ET
13
14
/C
S
14
15
SC
K
15
16
SD
ATA
16
17
P1
17
18
P0
18
19
VC
C
1
19
20
XO
U
T
20
21
XIN
21
23
23
24
24
25
25
26
26
27
27
28
28
29
29
31
31
34
34
42
42
41
41
40
40
1
1
22
VS
S
22
30
30
32
VP
32
33
33
35
35
36
36
37
37
38
38
39
39
43
43
44
44
45
45
46
46
47
47
48
48
IC1
M
6
60
04
FP
DG
1
2
DG
1
3
DG
1
4
DG
1
5
D0
D1
D2
D3
D4
D5
D6
VCC
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
X1
4.1
9
M
H
z
R12
1M
DSC
R29
33
DSO
/DCS
/DS
C
K
C19
10
0p
F
C20
0.1
u
F
-2
6V
C21
0.1
u
F
VCC
D34
D33
D32
D31
D30
D29
D28
D27
R39
2
7KG
C15
47
0p
F
/SH
E
N2
RES
C28
47
0p
F
C26
10
uF
1
0
V
/KR
3
/KR
2
/KR
1
/KR
0
DSC
VCC
VCC
VCC
VCC
SB
SC
SD
SE
SF
SG
DP
ID
AP
S1
/2
/SC
K
2
R60
C5
HTS2
ST
H2
R11
3
3
C6
C7
47
0p
F
X3
C8
0.1
u
F
C9
10
uF
/1
6V
C18
47
0p
F
VCC
C24
10
uF
/1
0V
R30
R31
33
X
2
1/2
3. Circuit diagram
8
7
6
5
4
3
2
1
A
B
C
D
1
2
3
4
5
6
7
8
D
C
B
A
2/2
VC
C
D1
SF
PB5
4
C3
4
1000
uF/
16V
R5
3
1.
2kF
ZD
2
R
D
5.
6PB
3
R4
7
3.
6kF
L7
180u
H
+20V
C3
0
220p
F
1
2
4
3
5
6
7
8
IC
3
MC34
063
R5
6
0.
22 1W
R5
7
+20V
C3
2
100u
F/5
0
V
1
2
3
4
5
6
7
8
9
10
CN
1
5301
5-
1
010
/R
ES
A
R
ESA
SC
K2A
/H
T
S
2
A
/STH
2A
SH
EN
2
VC
C
RE
S
L6
BL
M31
C3
7
470p
F
VC
C
VC
C
/R
ES
L1
BL
M31
R6
1
10K
1
2
IC
5
A
74LV
14A
3
4
IC
5
B
74LV
14A
/R
ES
A
R
ESA
VC
C
VC
C
R4
1
6.
2k
R4
4
4.
3k
7
6
1
3
1 2
IC
4
A
BA
10339
R5
4
15k
VC
C
C3
3
100u
F/1
6
V
R4
8
1
W
/0
.3
3
3
2
5
8
7
1
4
T1
C
EPH
1710
D2
SF
PL52
ZD
1
R
D
6.
2MB
R4
0
6.
8kF
Q1
2S
C3144
VF
1
VF
2
-26V
C3
1
100u
F/1
00V
ZD
3
R
D
39E
B7
VC
C
R4
5
1K
R4
3
13K
F
R4
6
10K
F
VC
C
VC
C
VC
C
VC
C
VC
C
VC
C
R4
9
10k
R5
0
10k
R4
2
51k
R5
1
100k
C2
9
330p
F
C3
5
0.
1uF
R5
2
1.
5k
9
8
14
3
1 2
IC
4
C
BA
10339
5
4
2
3
1 2
IC
4
B
BA
10339
11
10
13
3
1 2
IC
4
D
BA
10339
R5
5
2K
F
VC
C
L2
BL
M31
C3
9
470p
F
/S
CK
2
H
TS2
L3
BL
M31
C4
0
470p
F
ST
H2
L4
BL
M31
R6
3
10K
R6
4
10K
5
6
IC
5
C
74LV
14A
9
8
IC
5
D
74LV
14A
11
10
IC
5
E
74LV
14A
SC
K2A
/H
T
S
2
A
/STH
2A
L5
BL
M31
/S
HE
N
2
13
12
IC
5
F
74LV
14A
SH
EN
2A
C3
6
O
.O
15uF
R6
2
10K
C3
8
470p
F
8
7
6
5
4
3
2
1
A
B
C
D
1
2
3
4
5
6
7
8
D
C
B
A
4. PWB layout
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