Sharp UP-800 (serv.man19) Service Manual ▷ View online
UP-820N/820F (V)
CIRCUIT DIAGRAM
10 – 13
JTAG
Conn
ector i2.5V j
3-2Low
1-2High
FPGA Host & ROM i/f
Serial i/f (3/3)
to MCR CN
to JTAG CN
FPGA mode
FPGA Reset
Serial i/f (2/3)
TO CPU PWB
TO CPU PWB
2-3 SHORT SERI
A
L M
A
STER
1-2 SHORT BPI
& ADDRESS D
E
C
L
. M
O
D
E
SERIAL
FLASH MEMOR
Y&JT
AG CON : NOT MOUNT
1-2 SHOR
T
TDO
TM
S
IO_A21
IO_A20
IO_A19
IO_A18
IO_A17
IO_A16
IO_A15
IO_A14
IO_A13
IO_A12
IO_A1
1
IO_A10
IO_A9
IO_A8
IO_A7
IO_A6
IO_A5
IO_A4
IO_A3
IO_A2
IO_A1
TM
S
INIT_B
TM
S
TCK
INIT_B
IO_D0
DONE
TDO
IO_A21
IO_A20
IO_A19
IO_A18
IO_A17
FPGA_M1
FPGA_M0
FPGA_M2
IO_D6
IO_D1
IO_D0
IO_D7
IO_D5
IO_D3
IO_D2
IO_D15
IO_D4
KRQ#
LANINT#
FPGA_M2
FPGA_M1
FPGA_M0
IO_D15
CCLK
TDI
TCK
FPGA_RCP3#
FPGA_RCP2#
FPGA_RCP1#
FPGA_CLS3#
FPGA_CLS2#
FPGA_CLS1#
FPGA_RDD3#
FPGA_RDD2#
IO_A[1:21]
BYTE#
MS-FLASH_TDI
DONE
RESET#
FPGA_Ri3
FPGA_Ri2
FPGA_Ri1
FPGA_Ri4
FPGA_Ri5
FPGA_RCVDT3#
FPGA_RCVDT2#
FPGA_RCVDT1#
FPGA_RCVDT4#
FPGA_RCVDT5#
IO_D[0:15]
FPGA_OE#
FPGA_WE#
FPGA_CE#
KRQ#
LANINT#
FPGACS#
IO_RD#
IO_WE0#
FPGAINT#
A0
CKDC_SHEN#
2.5V
1.2V
3.3V
MCRINT
3
PROG_B
3.3V
2.5V
2.5V
1.2V
3.3V
3.3V
2.5V
1.2V
3.3V
2.5V
3.3V
3.3V
2.5V
3.3V
1.2V
3.3V
2.5V
1.2V
3.3V
2.5V
2.5V
3.3V
3.3V
C6
100pF
C33
0.1uF
R46
10K
IC6B
SN74L
V00APW
4
5
6
R60
0
R274
1
k
R53
0
C5
0.1uF
U1-2
XC3S25
0
E
-P
Q
2
0
8
54
55
56
57
58
60
61
63
74
75
76
77
78
80
81
82
83
84
86
87
90
93
94
96
97
99
100
101
102
103
104
53
59
62
64
65
66
67
68
69
70
71
72
73
79
85
88
89
91
92
95
98
CS5#
CSO_B
INIT_B
WR#
RD#
BUSY
CSI_B
RESET#
D7
D6
D5
D4
D3
RDWR_B
M2
D2
D1
M1
M0
D0
FIRQ#
A23
A22
A21
A20
A19
A18
EXINT4#
A17
CCLK
DONE
GND
VCCO
RI5
RI4
RI3
VCCAUX
VCCINT
RI2
RI1
GND
N.U.(INPUT)
N.U.(INPUT)
VCCO
GND
GND
VCCO
N.U.( I/O )
N.U.(INPUT)
VCCAUX
GND
N.U.( I/O )
R133
100
IC6A
SN74L
V00APW
1
2
3
14
7
U2
(XCF02S(TS
S
O
P
))
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
D0
(NC)
CLK
TDI
TMS
TCK
CF#
OE/RESET#
(NC)
CE#
GND
(NC)
CEO#
(NC)
(NC)
(NC)
TDO
VCCINT
VCCO
VCCJ
U1-1
XC3S25
0
E
-P
Q
2
0
8
106
107
108
109
11
0
11
2
11
3
11
5
11
6
11
9
120
122
123
124
126
127
128
129
130
132
133
134
135
136
137
138
139
140
142
144
145
146
147
148
150
151
152
153
154
155
105
111
11
4
11
7
11
8
121
125
131
141
143
149
156
A16
A15
A14
A13
EXINT3#
EXINT2#
EXINT1#
RCVDT5#
RCVDT4#
A12
A1
1
RCVDT3#
RCVDT2#
RCVDT1#
A10
A9
A8
A7
CLS3
A6
A5
A4
A3
RCP3
A2
A1
RDD3
A0
CLS2
RCP2
RDD2
MCRINT_N#
MCRINT
CLS1
HDC
LDC0
LDC1
LDC2
RCP1
TMS
GND
VCCAUX
VCCO
VCCINT
FPGA_A0
GND
VCCO
GND
GND
VCCO
VCCAUX
GND
R42
1
0
K
C29
0.1uF
R50
4
.7K
SP2
1-2 SHOR
T
1
3
2
R40
1
0
K
SP1
SHOR
T
PIN & SOCKET
1
3
2
C195
100pF
R41
1
0
K
(8
7831-14(M
O
LEX
))
CN6
14
12
10
8
6
4
2
13
11
9
7
5
3
1
NC
NC
TDI
TDO
TCK
TMS
VREF
GND
GND
GND
GND(CUT)
GND
GND
GND
C30
0.1uF
R51
4
.7K
R58
4
.7K
R55
0
D40
1SR159-200
1
2
R44
10K
C27
0.1uF
R49
10K
R48
10K
R59
4
.7K
C35
0.1uF
C31
10uF/10V
R45
10K
C32
0.1uF
C34
0.1uF
R47
3
3
R56
330
R43
1
0
K
R54
0
C28
10uF/10V
R52
0
C26
0.1uF
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
4/18
FPGA-1 (R
OM,HOST
-I/F)
UP-820N/820F (V)
CIRCUIT DIAGRAM
10 – 14
to JTAG CN
GPIO & Serial i/f
FPGA
to MCR i/f CN
Serial i/f (3/3)
cf. FPGA-section2
Serial i/f
(2/3)
cf. FPGA-section1
Serial i/f
(1/3)
DTC123EKA
3
1
2 BE
C
FPGA_SIN1
RMOT
OFF
JMOTCUP
RMOTCUP
PSENSON
FPGA_SIN2
FPGA_SIN3
FPGA_SIN4
FPGA_SIN5
GPIO14
GPIO15
GPIO16
GPIO28
GPIO30
GPIO29
GPIO31
GPIO32
GPIO14
GPIO15
GPIO16
GPIO28
JPES#
RPES#
STRB1#
STRB2#
STRB3#
STRB4#
ACUT1
ACUT2
JAS/MSTEP1
JDS/MSTEP2
RAS/MSTEP3
RDS/MSTEP4
JMOTCUP
RMOTCUP
VHCOM
PSENSON
INVPON
JMOT
OFF
RMOT
OFF
GPIO32
GPIO31
GPIO29
GPIO30
JMOT
OFF
JPES#
RPES#
STRB1#
STRB2#
STRB3#
STRB4#
TCK
MS-FLASH_TDI
TDI
FPGA_RDD1#
DCK
FPGA_DTR1
FPGA_SIN1
FPGA_SOUT1
FPGA_DSR1
FPGA_CTS1
FPGA_DCD1
FPGA_R
TS1
FPGA_DTR2
FPGA_SIN2
FPGA_SOUT2
FPGA_DSR2
FPGA_CTS2
FPGA_DCD2
FPGA_R
TS2
FPGA_DTR3
FPGA_SIN3
FPGA_SOUT3
FPGA_DSR3
FPGA_CTS3
FPGA_DCD3
FPGA_R
TS3
FPGA_DTR4
FPGA_SIN4
FPGA_SOUT4
FPGA_DSR4
FPGA_CTS4
FPGA_DCD4
FPGA_R
TS4
FPGA_DTR5
FPGA_SIN5
FPGA_SOUT5
FPGA_DSR5
FPGA_CTS5
FPGA_DCD5
FPGA_R
TS5
FPGA_RCVDT4#
FPGA_RCVDT5#
FPGA_RCVDT1#
FPGA_RCVDT2#
FPGA_RCVDT3#
CKDC_SRES#
DRA
W
ER1
DRA
W
ER2
JAS/MSTEP1
JDS/MSTEP2
RAS/MSTEP3
RDS/MSTEP4
PHUPS
ACUTSW
FPGA_DR
W
SNS
VHCOM
ACUT1
ACUT2
INVPON
FLASH_RESET#
3.3V
3.3V
1.2V
2.5V
PROG_B
2.5V
1.2V
3.3V
2.5V
2.5V
1.2V
3.3V
3.3V
1.2V
3.3V
2.5V
1.2V
3.3V
2.5V
3.3V
3.3V
3.3V
3.3V
R82
1
0
K
C42
0.1uF
R86
1
0
K
R101
10
K
R105
(10K)
R74
4.7K
R80
1
0
K
Q3
DTC123EKA
2
1
3
R92
10
K
IC6C
SN74L
V00APW
9
10
8
C40
0.1uF
C7
100pF
R106
10
K
R107
10K
R273
0(UP-810F)
R73
4.7K
C41
0.1uF
R69
0
R79
1
0
K
U1-4
XC3S25
0
E
-P
Q
2
0
8
157
158
159
161
162
163
164
165
167
168
169
171
172
174
175
177
178
179
180
181
183
184
185
186
187
189
190
192
193
194
196
197
199
200
202
203
204
205
206
207
160
166
170
173
176
182
188
191
195
198
201
208
TDO
TCK
RDD1
DCD5
RT
S
5
CTS5
DSR5
SIN5
DTR5
SOUT5
CTS4
RT
S
4
DCD4
DSR4
SIN4
CLK
DTR4
SOUT4
DCD3
RT
S
3
DSR3
SIN3
DTR3
SOUT3
DCD2
RT
S
2
CTS2
DTR2
DSR2
SIN2
SOUT2
DCD1
RT
S
1
CTS1
DTR1
DSR1
SIN1
SOUT1
HSW
A
P
TDI
CTS3
VCCAUX
VCCINT
GND
VCCO
GND
GND
VCCO
VCCAUX
GND
VCCO
GND
R99
10
K
R77
0
R104
10
K
R67
10K
Q2
DTC123EKA
2
1
3
R66
10K
R75
(4.7K)
R85
1
0
K
R81
1
0
K
R94
10
K
R68
10K
R83
1
0
K
R71
10K
R272
0(UP-800F)
R100
10
K
R270
0(UP-820N)
R97
1
0
K
R89
10
K
C39
0.1uF
U1-3
XC3S25
0
E
-P
Q
2
0
8
1
2
3
4
5
8
9
11
12
15
16
18
19
22
23
24
25
28
29
30
31
33
34
35
36
39
40
41
42
47
48
49
50
6
7
10
13
14
17
20
21
26
27
32
37
38
43
44
45
46
51
52
PROG_B
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO1
1
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
N.U.(INPUT)
VCCAUX
GND
VCCINT
N.U.(INPUT)
GND
N.U.(INPUT)
VCCO
N.U.(INPUT)
GND
N.U.(INPUT)
GND
VCCO
N.U.(INPUT)
VCCAUX
N.U.( I/O )
VCCO
N.U.(INPUT)
GND
R95
10
K
C37
0.1uF
R84
1
0
K
R90
1
0
K
R93
1
0
K
R63
10K
R91
1
0
K
R271
0(UP-820F)
C36
0.1uF
R96
(10K)
C15
100pF
R103
10
K
R76
0
C38
10uF/10V
R72
0
R88
1
0
K
R98
10K
R102
10
K
R65
10K
R78
0
IC6D
SN74L
V00APW
12
13
11
R64
10K
R87
1
0
K
R70
10K
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
5/18
FPGA-2 (GPIO
,SERIAL-I/F)
UP-820N/820F (V)
CIRCUIT DIAGRAM
10 – 15
to CPU PWB
to CPU PWB
to CPU PWB
MAC_EEPROM
LAN connector
modified 07,05,17
EEP_DIO
EEPCLK
EEP_DIO
EEP_CS
IO_A7
IO_A6
IO_A5
IO_A4
IO_A3
IO_A2
IO_A1
IO_D0
IO_D1
IO_D2
IO_D3
IO_D4
IO_D5
IO_D6
IO_D7
IO_D8
IO_D9
IO_D10
IO_D1
1
IO_D12
EEPCLK
EEP_CS
IO_D13
IO_D14
IO_D15
RD-
TD-
TD
+
RD+
IO_A8
IO_A9
IO_A10
IO_A1
1
IO_A12
IO_A13
IO_A14
IO_A15
IO_A16
IO_A17
IO_A18
IO_A19
IO_A20
IO_A21
RESET#
DACK1
IO_RD#
CS4#
IO_A[1:21]
IO_D[0:15]
LANINT#
3.3V
IO_WE1#
3.3V
3.3V
3.3V
VDD_A
3.3V
3.3V
3.3V
3.3V
VDD_A
VDD_PLL_1.8V
VDD_CORE_1.8V
3.3V
GND-FRAME
3.3V
R109
49.9(+-1
%
)
1
2
R381
(0) (3216)
1
2
C63
0.1uF
2
1
R1
1
8
0
1
2
C44
6.8nF
2
1
R120
(10K
)
C62
0.1uF
2
1
R1
1
5
(10K
)
C45
6.8nF
2
1
C61
0.1uF
2
1
C50
10uF 6.3V+-20%X5R
2
1
C47
33pF(50V 5%)
2
1
R1
10
49.9(+-1%
)
1
2
C66
0.1uF
2
1
C54
0.01uF
2
1
C52
10uF 6.3V+-20%X5R
2
1
C214
100pF
2
1
C49
0.1uF
C53
0.01uF
2
1
U3-1
LAN91
1
8rev
.A/[rev
.C]
18
17
16
15
14
13
12
94
64
63
62
59
58
57
56
53
52
51
50
49
46
45
44
43
40
39
38
37
36
33
32
31
30
29
26
25
24
23
22
21
72
70
92
95
93
9
69
68
67
87
76
98
99
100
71
73
75
84
10
74
82
83
78
79
6
5
A1
A2
A3
A4
A5
A6
A7
CS#
D0
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D1
1
D12
D13
D14
D15
D16/[TX_CLK]
D17/[TXD0]
D18/[TXD1]
D19/[TXD2]
D20/[TXD3]
D21/[COL]
D22/[CRS]
D23/[MDC]
D24/[MDIO]
D25/[RX_DV]
D26/[RX_CLK]
D27/[RX_ER]
D28/[RXD3]
D29/[RXD2]
D30/[RXD1]
D31/[TX_EN]
IRQ
PME
RD#
RESET#
WR#
A
TEST
EECLK
EECS#
EEDIO,D32/D16#
EXRES1
FIFO_SEL
LED1#/GPIO0
LED2#/GPIO1
LED3#/GPIO2
NC(1)
NC(2)
NC(3)/[RXD0]
NC(4)
RBIAS
SPEED_SEL
TPI-
TPI+
TPO-
TPO+
XT
AL1
XT
AL2
R385
0
1
2
MAC_EEPROM(93LC46A/SOIC-8)
U4
1
2
3
4
6
7
8
5
CS
SK
DI
DO
NC
NC
VCC
GND
R1
19
(1.00K) (1/10W 1%)
1
2
+
C59
22uF/16V(16SVP22M
)
1
2
R126
1.00K (1/10W 1%)
C57
0.1uF
2
1
C67
0.1uF
2
1
R123
0
1
2
C51
0.01uF
2
1
R1
12
49.9(+-1%
)
1
2
R124
12.0K(+-1%
)
1
2
C64
0.1uF
2
1
SI-60002-F
CN7
1
2
3
4
5
6
7
8
9
10
11
12
TCT
TD+
TD-
RD+
RD-
RCT
NC
GND
SH-1
SH-2
H1
H2
R1
1
4
10
K
1
2
R1
1
7
(10K
)
FB3
MMZ1608 (TDK)
1
2
R384
1M
1
2
C65
0.1uF
2
1
R125
(1.00K) (1/10W 1%)
R108
10.0(+-1%
)
1
2
C60
0.1uF
2
1
C43
0.022uF
2
1
R121
1
5
K
R382
0(321
6
)
1
2
R122
1.00K(+-1%
)
1
2
R1
1
6
(10K
)
1
2
C58
0.1uF
2
1
C55
0.1uF
2
1
C48
33pF(50V 5%)
2
1
X1
25MHz
(D
S
X
840G
A
)
1
2
C69
0.1uF
2
1
R386
0
1
2
R389
10
K
C46
0.01UF
2
1
C56
0.1uF
2
1
R1
13
12.4K (1/10W 1%)
1
2
R
111
49.9(+-1
%
)
1
2
C68
0.1uF
2
1
U3-2
LAN91
1
8rev
.A/[rev
.C]
81
85
89
91
3
65
20
28
35
42
48
55
61
97
7
8
2
2
1
66
19
27
34
41
47
54
60
96
77
80
86
88
90
4
11
VDD_A(1
)
VDD_A(2
)
VDD_A(3
)
VDD_A
_RB[NC]
VDD_CORE(1
)
VDD_CORE(2
)
VDD_IO(1)
VDD_IO(2)
VDD_IO(3)
VDD_IO(4)
VDD_IO(5)
VDD_IO(6)
VDD_IO(7)
VDD_IO(8)
VDD_PLL
VDD_REF
VREG
GND_CORE(1
)
GND_CORE(2
)
GND_IO(1
)
GND_IO(2
)
GND_IO(3
)
GND_IO(4
)
GND_IO(5
)
GND_IO(6
)
GND_IO(7
)
GND_IO(8
)
VSS_A(1)
VSS_A(2)
VSS_A(3)
VSS_A(4)
VSS_A_RB[NC]
VSS_PLL
VSS_REF
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
6/18
LAN contr
oler
UP-820N/820F (V)
CIRCUIT DIAGRAM
10 – 16
+
GND(1)
OUT(3)
IN(2)
CPU PWB
CKDC5V
CKDC 3V
INVERTER
to KEY IF PW
B
FPGA
& CPU
CPU PWB
FPGA
E
2
DTC114EKA
1
3
B
C
modified 07,05,11
modified 07,05,11
CKDC_KR3#
CKDC5_SC
CKDC5_SD
PG0
CKDC5_RESET
CKDC5_SF
CKDC5_STH
CKDC_KR2#
PG3
CKDC5_SG
CKDC5_SB
CKDC5_ST
OP#
CKDC5_SCK
PG2
PG1
CKDC5_SE
CKDC5_SHEN#
CKDC5_KRQ#
CKDC_KR0#
CKDC_KR1#
CKDC5_SDP
CKDC5_POFF#
CKDC5_HTS
KEX
0
KEX
1
ST3
ST2
ST1
ST0
CKDC5_KRQ#
CKDC5_SHEN#
CKDC5_STH
CKDC3_STH
CKDC3_SHEN#
CKDC3_KRQ#
CKDC5_SRES#
#
S
E
R
S
_
5
C
D
K
C
#
S
E
R
S
_
C
D
K
C
CKDC3_SRES#
CKDC5_ST
OP#
CKDC5_SCK
CKDC5_HTS
PG5
PG6
PG2
PG3
PG0
PG4
PG1
7SEG_5
7SEG_3
7SEG_1
7SEG_4
7SEG_6
7SEG_2
7SEG_0
CKDC5_SA
CKDC_P03
CKDC_P02
CKDC_P01
CKDC_P00
BUZZ
ST0
ST3
ST1
ST2
CKDC_KR2#
CKDC_KR1#
CKDC_KR3#
CKDC_KR0#
7SEG_6
7SEG_5
7SEG_4
7SEG_3
7SEG_2
7SEG_0
7SEG_1
MODR#
CFSR#
RESET#
CKDC_SHEN#
KRQ#
CKDC_STH
CKDC3_SRES#
CKDC3_KRQ#
CKDC3_SHEN#
CKDC3_STH
CKDC_HTS
CKDC_SCK
CKDC_ST
OP#
CKDC3_HTS
CKDC3_SCK
CKDC3_ST
OP#
CKDC_P02
CKDC_P01
CKDC_P00
CKDC_P03
CKDC_SRES#
DONE
CKDC_KR2#
CKDC_KR0#
CKDC_KR1#
CKDC_KR3#
CKDC5_SD
CKDC5_SA
CKDC5_SDP
CKDC5_SG
CKDC5_SF
CKDC5_SE
CKDC5_SC
CKDC5_SB
POFF#
CKDC5_POFF#
BUZZ
VLED
3.3V
ST3
CKDC_KR2#
KEX
1
CKDC_KR0#
CKDC_KR3#
ST2
CKDC_KR1#
KEX
0
ST0
ST1
CKDC5_SB
CKDC5_SDP
CKDC5_SD
CKDC5_SA
CKDC5_SG
CKDC5_SC
CKDC5_SF
CKDC5_SE
5VB
MODR#
5V
CFSR#
CKDC5_RESET
5V
3.3V
5V
5V
3.3V
5VB
5VB
5VB
3.3V
5V
3.3V
5.7V
3.3V
5V
5V
Q4
DTC1
14EKA
2
1
3
R156
(0)
R140
0
C88
(0.1uF)
R149
(0)
R129
(0)
IC8C
SN74HCT08PW
9
10
8
C82
(33pF)
X2
(32.768kHz)
1
2
R131
0
R146
47K
C83
(33pF)
C75
(470pF)
IC8A
SN74HCT08PW
1
2
3
14
7
RP3
10Kx4
3
2
1
2
1
4
5
6
7
8
6
7
8
R130
0
C72
100pF
R155
(47K)
+
C79
10uF/50V
TP1
C85
(33pF)
C74
(18pF)
R135
0
C189
100pF
R137
47K
R1
47K
C84
(33pF)
R128
(0)
R157
(47K)
J14
CON34
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
R206
47K
IC9
(CKDC9)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
53
54
55
56
57
58
59
60
61
62
63
64
SB
SC
SD
SE
SF
SG
P4
P0
P1
P2
P3
MODR
CFSR
KEX0
KEX1
RQ
SKR0
ST0
ST1
ST2
ST3
POFF
STO
P
DDIG
DCS
VCC
SCK
HTS
STH
SDISP
BUZZ
DSCK
SRES
DS0
SHEN
IRQ
KR0
KR1
KR2
KR3
RESET
OSC2
OSC1
GND
CL1
CL2
TEST
G0
G1
G2
G3
G4
G5
G6
G7
G8
G9
G5
G6
G7
G8
G9
G10
G11
G11
PO0
PO1
PO2
PO3
PO1
PO2
PO3
SA
RP6
0x4
3
2
1
4
5
6
7
8
R141
(0)
+
C87
(10uF/50V)
C70
100pF
C76
(1000pF)
C78
(100pF)
IC7C
SN74L
V08APW
9
10
8
R139
(0)
C77
(100pF)
BZ1
PKM22EPPH4002
1
2
R138
4.7K
R145
(0)
R275
1K
D1
1SS355
1
2
IC8D
SN74HCT08PW
12
13
11
RP5
0x4
3
2
1
4
5
6
7
8
RP4
10Kx4
3
2
1
2
1
4
5
6
7
8
6
7
8
R144
(1M)
RP8
0x4
3
2
1
4
5
6
7
8
R132
(0)
R142
47k
R136
4.7k
R276
3
3
R160
47K
IC7B
SN74L
V08APW
4
5
6
IC7A
SN74L
V08APW
1
2
3
14
7
C71
330pF
R143
47k
R150
(47K)
RP1
10Kx4
3
2
1
2
1
4
5
6
7
8
6
7
8
IC7D
SN74L
V08APW
12
13
11
R153
33
IC8B
SN74HCT08PW
4
5
6
RP2
(10Kx4)
3
2
1
2
1
4
5
6
7
8
6
7
8
R148
47K
R151
47K
RP7
0x4
3
2
1
4
5
6
7
8
C73
(15pF)
X3
(4.19MHz)
1
3
2
R127
(0)
R154
(47K)
C86
(470pF)
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
7/18
CKDC-1
Click on the first or last page to see other UP-800 (serv.man19) service manuals if exist.