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Data is transmitted from the host CPU to the TCP/IP board or vice
versa through the dual-port SRAM.  If data is written into the same
address of the dual-port SRAM from both sides or written into and
read from the same address from both sides, data is not assured.
The following procedure should be observed.

The format of data to be handled should meet the software specifica-
tions.

•

Interrupt signals from host to board :  Write/INTHW (Host Write),
Read/INTHR (Host Read)

/INTHW (Host Write) is generated by writing into the address
H’7*** of the dual-port SRAM and cancelled by outputting the
/HWACK signal by 100 ns LOW pulse.

/INTHR (Host Read) is generated by reading the address H’B*** of
the dual-port SRAM and cancelled by outputting the /HRACK sig-
nal by 100 ns LOW pulse.

•

Interrupt signals from board to host : Write /INTSW (Slave Write),
Read /INTSR (Slave Read)

/INTSW (Slave Write) is generated by outputting the /SWRQ sig-
nal by 100 ns LOW pulse and cancelled by writing data into the
address H’B*** of the dual-port SRAM from the host side..

/INTSR (Slave Read) is generated by outputting the /SRRQ signal
by 100 ns low pulse and cancelled by reading data from the
address H’7*** of the dual-port SRAM.

This board fixes RTL8019AS to the 8-bit mode on hardware.

The initial values of the items in the table are set as shown below by
hardware.

Item

Setting

Remarks

I/O Base Address

300H

IOS3~0

=

0,0,0,0

Network Media Type

TP/CX automatic
detection

PL1~0

=

0,0

BROM Size & Memory
Base Address

Disable

BS4~0

= 0,0,0,0,0

IRQ Select

INT0

IRQS2~0 =

0,0,0

Any data loading EEPROM is not used. MAC address should be
written by the CPU reading data on the flash memory and writing the
register of the LAN controller.

The common pins of the CPU are set as shown below. 

Pin

No

I/O

Selection

signal

Remarks

2

I

PE15

/WP(FLASH write STATUS)

24

I

/IRQ0

Host write end interrupt (   Edge detection)

25

I

/IRQ1

Host read end interrupt (   Edge detection)

26

I

/IRQ2

Interrupt from LANC (   Edge detection)

28

I

/IRQ3

Reserve (   Edge detection)

29

O

A18

Address Bus

30

O

A19

Address Bus

31

I

/WAIT

wait from LANC 

44

O

/CS3

Chip Select for LAN (Usual access space)

45

O

/CS2

Chip Select for dual-port SRAM

106

O

PE8

/SRRQ (Board side read end request)

107

O

PE9

/SWRQ (Board side write end request)

108

O

PE10

/HRACK
(host side read end interrupt cancel)

110

O

PE11

/HWACK
(host side write end interrupt cancel)

112

O

PE13

/RSTDRViActive Lowj

Write 

Y

N

Read 

Y

N

Preceding data read

 end interrupt?

Write data

Generation of write

end interrupt

Data write end 

interrupt?

Read data

Generation of read

end interrupt

AEN

SA19-SA0

SD7-SD0

IORB

IOWB

INT0

IOCHRDY

CPU

RTL8019AS

SLOT16

GND

/CS3

A19-A0

D7-D0

/RD

/WRL

/IRQ2

/WAIT

Pin No.

Signal name

Pin No.

Signal name

1

+5V

2

+5V

3

+5V

4

+5V

5

A15

6

A14

7

A13

8

A12

9

/DPCS

10

/WR

11

A11

12

A10

13

/RD

14

A0

15

A1

16

A2

17

A3

18

A4

19

A5

20

A6

21

A7

22

A8

23

A9

24

D7

25

D6

26

D5

27

D4

28

D3

29

D2

30

D1

31

D0

32

/LRES

33

/INTSR

34

/INTSW

35

NC

36

NC

37

GND

38

GND

39

GND

40

GND

Pin No.

Signal name

1

TX+

2

TX-

3

RX+

4

RX-

5

GND

Pin No.

Signal name

1

TX+

2

TX-

3

RX+

4

NC

5

NC

6

RX-

7

NC

8

NC

The board has two switches on it: program loading EPROM(Master ROM)
selection switch (SW1) and flash memory write protect switch (SW2).

The two switches are located on the board as shown below.

The factory setting of the switches are as follows:

Switch

Setting

Details of setting

SW1

4pin side

Boot from FLASH MEMORY

SW2

GND side

Write protect into FLASH MEMORY

SW1 selects booting from EPROM (Master ROM) to write program
data into flash memory.

When writing data from EPROM (Master ROM) to flash memory,
switch over to 6-pin side.

Usually, SW1 is set to marking side.

SW2 inhibits writing into flash memory.

When writing data from EPROM (Master ROM) to flash memory,
switch over to Vcc side.

Usually, the switch is set to the marking side.

SW1

SW2

4

5

6

1

2

3

FLASH

EPROM

SW1

Usual setting

Writing from EPROM
(Master ROM)

SW2

GN

D

VCC

Usual setting

Writing from EPROM (Master ROM)

1) Install the EPROM (Master ROM) to the UP-E10IN (IC5:IC

socket).

2) Set the following switches to the (Writing mode) on the UP-E10IN.

SW1 : [FLASH] 

 [EPROM]

SW2 : [GND] 

 [VCC]

3) Install the UP-E10IN to the ECR/POS (UP-600/700).

•

The ECR/POS (UP-600/700) power should be turned OFF.

4) Set the mode switch of the ECR/POS (UP-600/700) to SRV posi-

tion.

5) Turn ON the AC switch of the ECR/POS (UP-600/700).

6) Display : [SRV MODE]

Select the [5. DIAGNOSTIC] and press the ENTER key

Display : [5. DIAGNOSTIC]

Select the [TCP/IP] and press the ENTER key

Display : [TCP/IP]

Select the [MAC ADD&FIRM WRITE] and press the ENTER key

SW2

SW1:

IC5: IC socket

Normal mode

Writing mode

Normal mode

Writing mode

FLASH

EPROM

1

2

3

4

5

6

VCC

GND

SRV

0001

1

2

3

4

5

READING

SETTING

IRC SET UP

DOWN LOAD

DIAGNOSTIC

UP-600/700 DIAG V1.0A

PRODUCT & TEST

RAM & ROM & SSP

CLOCK & KEY & SWITCH

SERIAL I/O

DISPLAY & PRINTER

MCR & EFT & DRAWER

TCP/IP

TCP/IP & PRINTER DIAG

SELF Check

LOOPBACK Check

MAC ADDR & FIRM Ver. Read

MAC ADDR & FIRM WRITE

DATA Trans. (MA)

DATA Trans. (SA)

Display : [MAC ADD&FIRM WRITE] 

Input the MAC address and press the ENTER key.

•

MAC address:

The UP-E101N has a seal carrying a MAC address of hexadeci-
mal number attached on its CPU.
Enter this unique code (XXYYZZ) of hexadecimal number as the
values (3 values of 3 digits) converted to decimal numbers,
through the keyboard.
Example: When XX,YY,ZZ = 10,00,EB, enter 016,000,224 as

decimal numbers.

Start the writing of the MAC address & Firmware program

When writing is completed, the following message is displayed as
shown below.

Display :

7)

Press the CANCEL key to exit.

8)

Turn OFF the AC switch of the ECR/POS (UP-600/700).

9)

Remove the EPROM ( Master ROM) from the UP-E10IN (IC5:
IC socket).

10) Set the following switches to the (Normal mode) on the UP-

E10IN.

SW1 : [EPROM] 

 [FLASH]

SW2 : [VCC] 

 [GND]

11) Execute the "Service reset" .

MAC ADDR & FIRM Write

MAC ADDRESS:

AAA BBB CCC

08 00 1F XX YY ZZ

AAA BBB CCC
MAC Address : Decimal number

XX YY ZZ
MAC Address : Hexadecimal number

08001F
XXYYZZ

08001F : Fixed code

XXYYZZ : Unique code

MAC ADDRESS

IC1 CPU

SW1

SW2

MAC ADDR & FIRM Write

MAC ADDRESS:

AAA BBB CCC

08 00 1F XX YY ZZ

TCP/IP FIRM CHANGE:

FIRM CHANGE PASS!!