Sharp ER-A410 / ER-A420 (serv.man3) Service Manual ▷ View online
ER-A410/ER-A420
HARDWARE DESCRIPTION
– 11 –
6. KEY/DISPLAY
6-1. LCD CONTROL
The LCD control is the same as that of the ER-A275P.
LCD-related Register
<LCD Control Signal/Key Strobe Signal>
<Data Latch Signal> P94
L: LCD write data latch
6-2. KEY/DISPLAY SCAN
On A410/420, the key and display scan signal is common.
Key/display scan and key read are performed at the following timing.
1
Key/display scan cycle: 10ms
2
Blanking time: 50us
3
KEY DATA READ timing: 10 ~100us before turning off the strobe
signal
KEY DATA are read in two divisions by switching the exchange sig-
nal.
nal.
Key/Display-related Register
<LED Segment Signal> Write
<LCD Control Signal/Key Strobe Signal> Write
Bit3~0: KS3~0
At KS3~0, the strobe signals of KEY and POP UP Display are gener-
ated.
<Key Return Signal, Key Exchange Signal> Read Flat Keyboard
<Key Return Signal> Read Normal Keyboard
<Key Select Signal>
READ is performed at the timing of ST9 of CPU port P90 (Refer to 6-3.)
1: NORMAL KEY
0: FLAT KEY
The flat keyboard switches the key exchange signal and takes key data
in two times. For the reading timing, refer to the timing chart below.
in two times. For the reading timing, refer to the timing chart below.
The normal keyboard reads key data 10~100us before turning off the
strobe signal of the keyboard.
Function
Address
R/W
LCD Write Data
04001h
W
LCD Read Data
04002h
R
LCD Control Signal / Key Strobe Signal
04003h
W
Data Latch Signal
CPU port P94
W
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
04003h
–
E
R/W
RS
KS3
KS2
KS1
KS0
Bit7:
Not used
Bit6:
E
Enable Signal
Enable Signal
Enable
Bit5:
R/W
H: Data read L: Data Write
Bit4:
RS
H: Data input L: Instruction Input
RS
R/W
E
DB0-7
P94
DATA WRITE (CPU
3
LCD)
Valid Data
4003h
000xxxxx
WRITE
4001h
DATA
WRITE
4003h
010xxxxx
WRITE
4003h
000xxxxx
WRITE
4003h
001xxxxx
WRITE
RS
R/W
E
DB0-7
P94
DATA READ (CPU
1
LCD)
Valid Data
4003h
001xxxxx
WRITE
4003h
001xxxxx
WRITE
CPU
P94
HIGH
4003h
011xxxxx
WRITE
4002h
DATA
READ
4003h
001xxxxx
WRITE
CPU
P94
LOW
Function
Address
R/W
LED Segment Signal
04000h
W
LCD Control Signal / Key Strobe Signal
04003h
W
Key Return Signal
04003h
R
Key Exchange Signal
04003h Bit7
W
Key Select Signal
CPU port P90
R
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
04000h
dp
g
f
e
d
c
B
a
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
04003h
X
E
R/W
RS
KS3
KS2
KS1
KS0
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
04001h
X
X
X
X
KR11 KR10
KR9
KR8
04003h
KR7
KR6
KR5
KR4
KR3
KR2
KR1
KR0
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
04003h
KR7
KR6
KR5
KR4
KR3
KR2
KR1
KR0
950
m
25us
50
m
5us
Max. 10us
10~100us
Fh
Fh
Fh
BLANK
BLANK
BLANK
1ST DIGIT
DISPLAY DATA
2ND DIGIT
DISPLAY DATA
1ST DIGIT
DISPLAY DATA
0
1
9
0
KS0~3
LED Segment
Signal
Signal
Key Return
Signal
Signal
ER-A410/ER-A420
HARDWARE DESCRIPTION
– 12 –
6-3. OTHERS
The MODE key switch and other sensor signals are read with the CPU
port P90 and 91 at the keyboard strobe timing. Reading is performed
10~100us before turning off the strobe signal.
6-4. DISPLAY
The ER-A410/A420 is provided with the front LCD of 5 x 7dot, 2 lines 16
digits, and the 7-digit LED on the pop up side.
digits, and the 7-digit LED on the pop up side.
FRONT:
POP UP:
• DISPLAY DIGIT SIGNAL
The above ST0~ST6 are DIGIT signals.
ST0: 1st digit~ST6:7th digit
• DISPLAY SEGMENT SIGNAL (REFER TO 6-2.)
By writing segment data to 4000h, the LED segment signal can be
outputted.
DATA~SEGMENT correspondence
7. EFT I/F
The ER-A410/A420 can be connected with the EFT I/F PWB as an
option.
option.
The EFT I/F is mapped in the /CS3 area.
By inserting the EFT PWB, the RS-232 CH2 signal is switched to the
signal from the EFT.
signal from the EFT.
Since, however, the reception data (RTX) of RS232 CH2 is inputted to
the CPU without being cut, the CPU port must be set so that the input
can be received without problems. The EFT PWB unit is common
can be received without problems. The EFT PWB unit is common
except for the EFT section of the ER-01EF and the I/O address from the
HOST.
7-1. EFT I/F
X: Not fixed (EFT
3
ECR just before)
1
Data read of SUB CPU 1: Not reading 0: Reading
2
Data to SUB CPU 1: YES 0: NO
3
Data to HOST CPU 1: YES 0: NO
EFT RESET
RESET signal to initialize the EFT I/F.
After resetting the machine, /EFTRST is outputted at LOW for more
than 10
µ
sec.
During LOW period, the EFT I/F should not be accessed.
EFT CONNECT SIGNAL
EFT I/F connect signal 0: EFT PWB provided 1: EFT PWB not provided
CPU
STO
ST1
ST2
ST3
ST4
ST5
ST6
ST7
ST8
ST9
MODE
P90
SRV
PGM
VOID
OP X/Z
REG
MGR
X1/Z1
X2/Z2
Key Select
OTHERS
P91
PF-R
PF-J
RPE
HEAD UP
JPE
DRAWER
OPEN
RS1_CI
P90
ST0 : MODE Key SRV
“0” SRV mode
ST1 : MODE Key PGM
“0” PGM mode
ST2 : MODE Key VOID
“0” VOID mode
ST3 : MODE Key OP X/Z
“0” OP X/Z mode
ST4 : MODE Key REG
“0” REG mode
ST5 : MODE Key MGR
“0” MGR mode
ST6 : MODE Key X1/Z1
“0” X1/Z1 mode
ST7 : MODE Key X2/Z2
“0” X2/Z2 mode
ST9 : Keyboard select
“0” Flat key
“1” Normal key
P91
ST0 : Receipt feed
“0” Receipt feed
ST1 : Journal feed
“0” Journal feed
ST2 : Receipt paper end
“1” Receipt paper end
ST3 : Head up
“0” Head up
ST4 : Journal paper end
“1” Journal paper end
ST6 : Drawer open sensor
“0” Drawer open
ST9 : RS-232 ch1 CI signal
D0~D6
3
a~g
D7
3
DP
HOST CPU
I/O address
I/O address
Name
0400EH
DTR
Used for data send/receive to/from
the EFT I/F CPU.
the EFT I/F CPU.
(Data register)
When WRITE: ECR
3
EFT
When READ: EFT
3
ECR
READ/WRITE should be per-
formed only when the condition of
NOTE 1 is satisfied.
formed only when the condition of
NOTE 1 is satisfied.
0400FH
STR
Used for data send/receive to/from
the EFT I/F CPU.
the EFT I/F CPU.
(Status register) When WRITE: Indicates the EFT I/F
status.
When READ: EFT sub system reset
control
control
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
CLM
IBF
OBF
1
2
3
NOTE 1) Data write to DTR is performed when “CLM:1/IBF:0.”
Data read from DTR is performed when “OBF:1.”
Pin No.
CPU PORT
Signal to be used
33
P65
/EFTRST
Pin No.
CPU PORT
Signal to be used
19
P83
/EFTC
ER-A410/ER-A420
HARDWARE DESCRIPTION
– 13 –
7-2. EFT I/F CONNECTOR SPECIFICATIONS
8. SERIAL I/O
The ER-23X is provided with 2ch of RS-232 PORTs as standard provi-
sion. 1ch of the two is switched with the EFT I/F.
sion. 1ch of the two is switched with the EFT I/F.
The RS-232 ch1 and ch2 are assigned to the following CPU port and I/
O.
O.
Ch1
Ch2
<Serial I/O ch2 receive signal> Read
RS-232/EFT I/F BLOCK DIAGRAM
9. POWER
10. FLASH MEMORY REWRITE PROCEDURE
11. DRAWER
The ER-A410/A420 is provided with 2CH of DRAWER ports.
The DRAWER solenoid energizing time is as shown below.
50ms (max) 45ms(min)
GND
1
2
GND
GND
3
4
GND
A0
5
6
A1
A2
7
8
A3
A4
9
10
A5
VCC
11
12
VCC
/RD
13
14
/WR
/CS3
15
16
D0
17
18
D1
D2
19
20
D3
D4
21
2
D5
D6
23
24
D7
25
26
/EFTRES
/EFT_CD
27
28
EFT_RD
EFT_SD
29
30
/EFT_ER
/EFT_DR
31
32
/EFT_RS
/EFT_CS
33
34
/EFT_CI
/POFF
35
36
/EFTS
GND
37
38
GND
GND
39
40
GND
Pin No.
CPU PORT
Signal to be used
34
/RTS1
/RS1
32
RXD1
RD1
31
TXD1
SD1
26
P74
/ER1
25
P75
/CD1
24
P76
/CS1
23
P77
/DR1
6
P91 (Refer to 6-3.)
/CI1
Pin No.
CPU PORT
Signal to be used
38
/RTS0
/RS2
36
RXD0
RD2
35
TXD0
SD2
18
P84
/ER2
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bir1
Bit0
04000h
X
X
X
X
/CD2
/DR2
/CS2
/CI2
IPL from EP-ROM: Set the IPL SW to ON and turn on the power, and
the EP-ROM will be boosted.
The bank of the EP-ROM program is switched
through S-RAM to transfer the program to the
FLASH ROM.
FLASH ROM.
IPL from COM:
Data from PC is written through the COM port to
the FLASH ROM. (Max. 38.4kbps)
CPU
Ch1 connector
Ch2 connector
MUX
EFT I/F PWB
B
AA/B
Y
+5V
Service interruption should be performed
within 10ms after generation of /POFF.
within 10ms after generation of /POFF.
TRANS.
LM2574 + TR
24V
DRAWER
PRINTER
PRINTER
ON/OFF control
(MODE SW)
(MODE SW)
PQ1CG2032
VLED 5.7V
VCC 5.0V
VDD 5.0V
BATTERY
/POFF detection point
ER-A410/ER-A420
HARDWARE DESCRIPTION
– 14 –
12. PRINT RATIO LIMITATION
Max. 288dot/1line x 140line (Corresponds to black background LOGO
print.)
Ave. 108dot/1line or less (Corresponds to 12.5% of all dots.)
13. BUZZER
A buzzer of piezo type is used.
The oscillation frequency is 4.0kHz
m
0.5kHz.
14. RESET
The RESET signal is generated under the following condition.
1) When the MODE KEY SWITCH is moved from SRV’ to another
position (except for OFF).
15. POFF
The POFF signal is changed from 0 to 1 when the 5V system power
and the 24V system power reach the operating voltage. When they fall
and the 24V system power reach the operating voltage. When they fall
below the operating voltage, the signal is changed from 1 to 0.
POFF, RESET TIMING CHART
16. I/O
<LED Segment Signal> Write
<Serial I/O ch2 receive signal> Read
<LCD Write Data> Write
<Key Return Signal, Key Exchange Signal> Read
<LCD Read Data> Read
<LCD Control Signal/Key Strobe Signal> Write
<Key Return Signal> Read
<LCD Control Signal/Key Strobe Signal> Write
<EFT Data> Write/Read
<EFT Status> Read
+5V
+24V
/RESET
/POFF
/EFTRES
20.8V
POWER ON
Instant service
interruption
interruption
MODE
SRV'
SRV'
MODE
Other than
SRV'
Other than
SRV'
POWER OFF
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
04000h
dp
g
f
e
d
c
B
a
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
04000h
X
X
X
X
/CD2
/DR2
/CS2
/CI2
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
04001h
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
04001h
X
X
X
X
KR11 KR10
KR9
KR8
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
04002h
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
04003h
X
E
R/W
RS
KS3
KS2
KS1
KS0
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
04003h
KR7
KR6
KR5
KR4
KR3
KR2
KR1
KR0
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
04003h
X
E
R/W
RS
KS3
KS2
KS1
KS0
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0400Eh
D7
D6
D5
D4
D3
D2
D1
D0
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0400Fh
X
X
X
X
X
CLM
IBF
OBF
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