Sharp DV-620 (serv.man12) Service Manual ▷ View online
37
DV-620H
DV-620S
DV-620S
10-12. IC8201 IX1610GE SUB CPU
Pin Name
Input/Output
Functions
R43 to R40
I/O
4-bit I/O port with latch.
When used as input port, the latch must be set to "1".
When used as input port, the latch must be set to "1".
R53 to R50
Every bit data is possible to be set cleared and tested by the bit manipulation instruction of the
L-register indirect addressing.
L-register indirect addressing.
R81 (T2)
2-bit I/O port with latch.
Timer/Counter 2 external input
I/O(Input)
When used as input port, external interrupt input
R80 (INT2)
pin, or timer/counter external input pin, the latch
External interrupt 2 input
must be set to "1".
XIN
Input
Resonator connecting pins.
XOUT
Output
For inputting external clock, XIN is used and XOUT is opened.
RESET
Input
Reset signal input
HOLD(INT1)
I/O(Input)
Hold request/release signal input
External interrupt 1 input and R82 I/O
VDD
Power Supply
+5V
Vss
0V (GND)
• Block Diagram
Hold controller
System controller
Timing Generator
Clock Generator
Interval Timer
12-bit
Timer/Counter
(2ch)
Timer/Counter
(2ch)
C Z S G
FLAG
ALU
KE
Accumulator
HR
LR
RAM Address buffer
Data Memory
(RAM)
Program
Counter
Counter
IR register
IR Decoder
EIR
Interrupt controller
EIF
Stack
SPW
DC
TC2
TC1
R5
R53
to
R50
R4
R43
to
R40
R8
R81 (T2)
R80 (INT2)
R80 (INT2)
I/O
port
port
I/O port
(R4 is High current port)
T/C input
Interrupt input
Interrupt input
Program
Memory (ROM)
Memory (ROM)
VDD
VSS
HOLD
(INT1)
RESET
Power Supply
XIN
XOUT
XOUT
Osc. connecting
pins
pins
Hold input
Reset input
DV-620H
DV-620S
DV-620S
38
10-13. IC201 MC44724A DIGITAL VIDEO ENCODER
Pin No.
Terminal name
I/O
Operation function
1
CVBS/Cb/B1
O
Analog composite video signal output or Cb or B signal output current drive (positive)
2
CVBS/Cb/B1
O
Analog composite video signal output or Cb or B signal output current drive (negative)
3
CVBS/Cb/B1 Vdd
Power Supply for CVBS / Cb/B DAC1 circuit
4
Y/G 1
O
Analog luminance or G signal output current drive (positive)
5
Y/G 1
O
Analog luminance or G signal output current drive (negative)
6
Y/G 1Vdd
Power Supply for Y/G DAC1 circuit
7
C/Cr/R 1
O
Analog chrominance signal output or Cr or R signal output current drive (positive)
8
C/Cr/R 1
O
Analog chrominance signal output or Cr or R signal output current drive (negative)
9
C/Cr/R 1Vdd
Power Supply for C/Cr/R DAC1 circuit
10
DA Vss
Ground for DAC circuit
11
Ibias 1
O
Reference current for the 1st set of 3 DACs
12
VRef 1
Reference full scale voltage for the 1st set of 3 DACs
13
DA Vdd
Power Supply for DACs
14
VRef 2
Reference full scale voltage for the 2nd set of 3 DACs
15
Ibias 2
O
Reference current for 2nd set of the 3 DACs
16
NC
No connect to pin
17
CVBS/Cb/B2
O
Analog composite video signal output or Cb or B signal output current drive (positive)
18
CVBS/Cb/B2
O
Analog composite video signal output or Cb or B signal output current drive (negative)
19
CVBS/Cb/B2 Vdd
Power Supply for CVBS / Cb/B DAC2 circuit
20
Y/G 2
O
Analog luminance or G signal output current drive (positive)
21
Y/G 2
O
Analog luminance or G signal output current drive (negative)
22
Y/G Vdd
Power Supply for Y/G DAC2 circuit
23
C/Cr/R 2
O
Analog chrominance signal output or Cr or R signal output current drive (positive)
24
C/Cr/R 2
O
Analog chrominance signal output or Cr or R signal output current drive (negative)
25
C/Cr/R 2Vdd
Power Supply for C/Cr/R DAC2 circuit
26
ChipA
I2C chip address select {0 : 40(hex)/41(hex) 1 : 1D(hex)/1E(hex)}
27
TEST
I
TEST pin (Ground)
28
DVss
Ground for Digital circuit
29
CLOCK
I
27MHz clock input
30
DVdd
Power Supply for Digital circuit
31
Reset
I
Reset signal, active LOW
32
PAL/NTSC
I
NTSC/PAL select. This pin is sampledonly at Reset.(NTSC : Low PAL : High)
33
SO
z(O)
In SPI mode, serial data output / In I2C mode, grounded.
34
SDA/SI
I/O(I)
Serial data input, Open drain output / If SPI mode, serial data input
35
SCL/SCK
I
Serial clock
36
SEL
I/(I)
Connect to Ground / If SPI mode, this pin is chip select
37
DVdd
Power supply for Digital circuit
38
DVss
Ground for Digital circuit
39-46
DVIA7-0
I/O
8-bit Multiplexd Y/Cr/Cb 4:2:2 data (ITU Rec656/601) input (DVIA) or Multiplexd Y data
(ITU-Rec656/601) input in 16-bit input mode
(ITU-Rec656/601) input in 16-bit input mode
47
Vmute
I
Video mute on Reset (0: normal, 1: mute)
48
C/Fsync/VBI
I/O
Csync/Frame sync input/output
49
F/Vsync
I/O
Frame sync or Vertical sync input/output
50
Hsync
I/O
Horizontal sync input/output
51
A/B sel
I
Switch control for 8-bit x 2 Mutiplexed 4:2:2 data (ITU Rec656/601) input (DVIA) or (DVIB)
52-55
DVIB7-4
I/O
8-bit Multiplexed 4:2:2 data (ITU Rec656-601) input (DVIB), or Multiplexed Cr/Cb data
(ITU Rec656/601) input in 16-bit input mode
(ITU Rec656/601) input in 16-bit input mode
56
DVss
Ground for Digital circuit
57
DVdd
Power Supply for Digital circuit
58-61
DVIB3-0
I/O
Multiplexed 4:2:2 data (ITU Rec656/601) input (DVIB), or Multiplexed Cr/Cb data
(ITU Rec656/601) input in 16-bit input mode
(ITU Rec656/601) input in 16-bit input mode
62
TP
I/O
Test data input/output (Grounded)
63,64
NC
No connect to pin (Ground)
39
DV-620H
DV-620S
DV-620S
• Block Diagram
H, V
Y
demux
Cb
Cr
Modulator
subcarrier
gen
off_set
0
0
0
CGMS,
WSS gen
CC_gen
Sync_generator
BG
copy
protection
bus
bus
TEST
I2C/SPI
BIAS
DAC
DAC
DAC
30 37, 57
28
51
38, 56
39~46
52~55, 58~61
DVdd
DVss
DVIA [7:0]
DVIB [7:0]
A/B_sel
62
TP
29
Clock
26
Chip A
31
Reset
32
33
PAL/NTSC
SO
34
SDA/SI
35
SCL/SCK
36
SEL
27
TEST
10
DAVss
13
DAVdd
15
Ibias 2
14
Vref 2
24
C/Cr/R 2
23
C/Cr/R 2
18
CVBS/Cb/B 2
17
CVBS/Cb/B 2
21
Y/G 2
20
Y/G 2
11
Ibias 1
12
Vref 1
8
C/Cr/R 1
7
C/Cr/R 1
2
CVBS/Cb/B 1
1
CVBS/Cb/B 1
5
Y/G 1
4
Y/G 1
9
C/Cr/R 1Vdd
3
CVBS/Cb/B 1Vdd
6
Y/G 1Vdd
25
C/Cr/R 2Vdd
19
CVBS/Cb/B 2Vdd
22
Y/G Vdd
50
Hsync
49
F/Vsync
48
C/Fsync/VBI
MC44724/5A
BIAS
DAC
DAC
Output Selector
DAC
0
0
0
0
0
0
0
RGB matrix
DV-620H
DV-620S
DV-620S
DV-620H
DV-620S
DV-620S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
B
C
D
E
F
G
H
I
J
40~41
11. BLOCK DIAGRAMS
11-1. MAIN BLOCK DIAGRAM
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