Sharp DV-620 (serv.man12) Service Manual ▷ View online
33
DV-620H
DV-620S
DV-620S
35
CLK
Clock
The system clock input. All other inputs are referenced to the SDRAM on
the rising edge of CLK.
the rising edge of CLK.
34
CKE
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will
be one of the states among power down, suspend or self refresh.
be one of the states among power down, suspend or self refresh.
18
CS
Chip Select
Command input enable or mask except CLK, CKE and DQM
19
BS
Bank Address
Select either one of banks during both RAS and CAS activity.
20~24
A0~A10
Address
Row Address: RA0~RA10, Column Address: CA0~CA7
27~32
Auto-precharge flag:A10
17, 16, 15
RAS, CAS, WE
Row Address Strobe,
RAS, CAS and WE define the operation.
Column Address Strobe,
Refer function truth table for details.
Write Enable
14, 36
DOML, DOMU
Data Input/Output Mask
DOM control output buffer in read mode and mask input data in write mode.
2, 3, 5,
I/O0~15
Data Input/Output
Multiplexed data input/output pin
6, 8, 9, 11, 12, 39, 40,
42, 43, 45, 46, 48, 49
42, 43, 45, 46, 48, 49
VCC/VSS
Power Supply/Ground
Power supply for internal circuit and input buffer.
1, 25, 26
4, 7, 10,
VCCO/VSSO
Data Output Power/Ground Power supply for DO
13, 38, 41, 44, 47, 50
33, 37
NC
No Connection
No connection
10-8. IC602-3 IX3455CE 16M SDRAM
Terminal
Terminal Name
Name
Input Function
• Block Diagram
Refresh
Interval Timer
Refresh
Counter
Self Refresh Counter
Address
Register
Register
Burst Length
Counter
Column Addr.
Latch & Counter
512Kx16
Bank 1
Column Decoder
Sense AMP & I/O gates
Column Decoder
Sense AMP & I/O gates
Mode Register
Test Mode
I/O Control
512Kx16
Bank 0
Row Addr. Latch/Predecode
Row Addr. Latch/Predecode
State Machine
Data Input/Output Buffers
Row Decoder
Precharge
Row Active
Column Active
Overflow
Address[0:10]
Audio/Self Refresh
Ref. Addr.[0:11]
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
CLK
CKE
BS(A11)
CS
RAS
CAS
WE
DOMU
DOML
DV-620H
DV-620S
DV-620S
34
• Block Diagram
10-9. IC702 BA5984FP
MOTOR DRIVER
Pin No.
Terminal name
Operation function
Pin No. Terminal name
Operation function
1
FWD
Loading driver FWD input terminal
15
VO4(+)
Driver CH4 Negative output
2
OPIN1(+)
CH1 Former stage amplifier nonreverse input terminal
16
VO4(-)
Driver CH4 Positive output
3
OPIN1(-)
CH1 Former stage amplifier reverse input terminal
17
VO3(-)
Driver CH3 Positive output
4
OPOUT1
CH1 Former stage amplifier output terminal
18
VO3(+)
Driver CH3 Negative output
5
OPIN2(+)
CH2 Former stage amplifier nonreverse input terminal
19
GND
Ground terminal
6
OPIN2(-)
CH2 Former stage amplifier reverse input terminal
20
BIAS
Bias input terminal
7
OPOUT2
CH2 Former stage amplifier output terminal
21
MUTE
Mute control terminal
8
VCC
Power terminal
22
OPOUT3
CH3 Former stage amplifier output terminal
9
VOL(-)
Loading driver Negative output
23
OPIN3(-)
CH3 Former stage amplifier reverse input terminal
10
VOL(+)
Loading driver Positive output
24
OPIN3(+)
CH3 Former stage amplifier nonreverse input terminal
11
VO2(-)
Driver CH2 Negative output
25
OPOUT4
CH4 Former stage amplifier output terminal
12
VO2(+)
Driver CH2 Positive output
26
OPIN4(-)
CH4 Former stage amplifier reverse input terminal
13
VO1(-)
Driver CH1 Negative output
27
OPIN4(+)
CH4 Former stage amplifier nonreverse input terminal
14
VO1(+)
Driver CH1 Positive output
28
REV
Loading driver REV input terminal
Note 1: Positive and negative output the driver have polarity with respect to input. (An example: 4 pin terminal voltage
‘HIGH’: 14 pin terminal voltage ‘HIGH’)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
-
+
-
+
10K
10K
16K
16K
-
+
-
+
10K
16K
10K
16K
MUTE
REV OUTF
FWD OUTR
FWD OUTR
Loading Driver
VCC
10K
10K
10K
10K
10K
10K
10K
10K
- +
Level
Shift
- +
Level
Shift
10K
10K
10K
10K
10K
10K
10K
10K
- +
Level
Shift
- +
Level
Shift
+ -
+ -
- +
- +
-+
-+
- +
- +
-+
-+
+ -
+ -
35
DV-620H
DV-620S
DV-620S
Pin No.
Terminal name
I/O
Operation function
1-4
SW1 to SW4
I
General purpose input pins
5
DOUT
O
Data output pin (N-Channel, Open-Drain)
This pin outputs serial data at the falling edge of the shift clock (starting from the lower bit).
This pin outputs serial data at the falling edge of the shift clock (starting from the lower bit).
6
DIN
I
Data input pin
This pin inputs serial data at the rising edge of the shift clock (starting from the lower bit)
This pin inputs serial data at the rising edge of the shift clock (starting from the lower bit)
7, 43
GND
–
Ground pin
8
CLK
I
Clock input pin
This pin reads serial data at the rising edge and outputs data at the falling edge.
This pin reads serial data at the rising edge and outputs data at the falling edge.
9
STB
I
Serial interface strobe pin
The data input after the STB has fallen is processed as a command.
When this pin is "HIGH", CLK is ignored.
The data input after the STB has fallen is processed as a command.
When this pin is "HIGH", CLK is ignored.
10-13
K1 to K4
I
Key data input pins
The data inputted to these pins are latched at the end of the display cycle.
The data inputted to these pins are latched at the end of the display cycle.
14, 38
VDD
–
Logic power supply
15-20
SG1/KS1 to
O
High-voltage segment output pins also acts as the key source
SG6/KS6
21-25
SG7 to SG11
O
High voltage segment output pin
26, 28-31
SG12/GR11
High voltage segment/grid output pins
SG13/GR10 to
O
SG16/GR7
27
VEE
–
Pull-down level
32-37
GR6 to GR1
O
High-voltage grid output pins
42-39
LED1 to LED4
O
LED output pin
44
OSC
I
Osillator input pin
A resistor is connected to this pin to determine the oscillation frequency.
A resistor is connected to this pin to determine the oscillation frequency.
10-10. IC5001 PT6312LQ
FL DRIVER
• Block Diagram
Serial
Data
Interface
Control
Segment
Driver/
Grid
Driver/
Key Scan
Output
Grid
Driver
Dimming Circuit
Timing Generator
Key Matrix Memory
Display Memory
(16bits x 11 Words)
OSC
General
Input
Register
LED
Driver
10 11 12 13
14, 38 7, 43
27
VDD
GND
VEE
K1 K2 K3 K4
SW1
SW2
SW3
SW4
LED1
LED2
LED3
LED4
1
6
5
8
9
42
41
40
39
2
3
4
OSC
VDD
R
DIN
DOUT
CLK
STB
44
15
16
17
18
19
20
21
22
23
24
25
26
28
29
30
31
37
36
35
36
35
34
33
32
32
GR1
GR2
GR3
GR4
GR5
GR6
SG12/GR11
SG13/GR10
SG14/GR9
SG15/GR8
SG16/GR7
SG1/KS1
SG2/KS2
SG3/KS3
SG4/KS4
SG5/KS5
SG6/KS6
SG7
SG8
SG9
SG10
SG11
DV-620H
DV-620S
DV-620S
36
Pin No.
Terminal name
I/O
Operation function
1
LRCIN
I
LRCK clock input (fs)
(3)
2
DIN
I
Data input
(3)
3
BCKI
I
Bit clock input for data.
4
CLKO
O
System clock buffered output.
5
XTI
I
Connection of crystal oscillator or external clock input.
6
XTO
O
Connection of crystal oscillator
7
DGND
–
Digital GND
8
V
DD
–
Digital power +5V
9
V
CC
2R
–
Analog power +5V
10
AGNDR
–
Analog GND
11
EXTR
O
Rch Analog output amp. • common
12
NC
–
Not connected.
13
V
OUT
R
O
Rch Analog voltage output
14
AGND
–
Analog GND
15
V
CC
–
Analog power +5V
16
V
OUT
L
O
Lch Analog voltage output
17
NC
–
Not connected.
18
EXTL
O
Lch Analog output amp. • common
19
AGNDL
–
Analog GND
20
V
CC
2L
–
Analog power +5V
21
ZERO
O
Zero data • flug
22
RSTB
I
Resetting. While this pin is in "L" state, the DF and delta -sigma modulator is in reset state.
(1)
23
CS/IWO
I
Chip selection/input format selection
(2)
24
MODE
I
Mode control selection (H: Software, L: Hardware)
(1)
25
MUTE
I
Mute control
(1)
26
MD/DM0
I
Mode control data/deemphasis selection 1
(1)
27
MC/DM1
I
Mode control BCK/deemphasis selection 2
(2)
28
ML/IIS
I
Mode control latch/input format selection
(1)
Note: (1) Pins 22, 24, 25, 26, 27, and 28: With Schmidt trigger input pull-up resistor (2) Pin 23: With Schmidt trigger input pull-down resistor
(3) Pins 1, 2, and 3: Schmidt trigger input
10-11. IC6001 PCM1716E
AUDIO DAC
• Block Diagram
BCKI
LRCIN
DIN
ML/IIS
MC/DM1
MD/DM0
MD/DM0
CS/IWO
MODE
MUTE
RSTB
Sirial
Input
Input
I/F
Mode
Control
I/F
XTI XTO
CLKO
V
CC
AGND
DGND
V
DD
Power
BPZ-Cont.
Crystal OSC
8-time oversampling
digital filter with
function controller
Multilevel
delta/sigma
modulator
DAC
20 19
9
10
DAC
Low-pass
filter
Low-pass
filter
V
OUT
L
V
CC
2L
AGNDL
V
CC
2R
AGND
R
EXTL
EXTR
V
OUT
R
ZERO
Open Drain
16
18
13
11
21
7
8
4
6
5
14
15
22
25
24
23
26
27
28
2
1
3
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