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XL-UR27H

8 – 5

49

Pio1

Input / Output

3I/F

DSP general input/output port -1.

Input

Schmitt input CMOS PORT

50

Pio2

Input / Output

3I/F

DSP general input/output port -2.

Input

Schmitt input CMOS PORT

51

Pio3

Input / Output

3I/F

DSP general input/output port -3.

Input

Schmitt input CMOS PORT

52

VSS

-

Grounding pin for 3.3V digital circuit.

-

-

53

VDDT3

-

Power supply pin for 3.3 V digital I/O circuit.

-

For CD and DSP I/O

54

SBSK

Output 3AI/F

Sub code block sync output pin.

Output

CMOS PORT

55

SBOK

Output 3I/F

CRCC check result output pin for sub code Q data.

Output

CMOS PORT

56

IPF

Output 3I/F

Correction flag output.

Output

CMOS PORT

57

SFSY

Output 3I/F

Servo internal register read clock output pin.

Output

CMOS PORT

58

ZDET

Output 3I/F

Internal Audio DAC Zero data detection flag output.

Output

CMOS PORT

59

GPIN

Input 3I/F

CD General Input port (Pull down by 100K

Ω when not 

in use).

Input

Schmitt input

60

MS

Input 3I/F

Microprocessor I/F mode selection pin.
“H”: Parallel I/F, “L”: Serial I/F

Input

61

DoUT(Po6)

Output 3I/F

Digital Audio output (SPDIF) pin
(DSP general output port -6)

Output

CMOS PORT

62

AoUT1(Po7)

Output 3I/F

Audio data output pin -1 
(DSP general output port -7)

Output

CMOS PORT

63

BCKo(Po8)

Output 3I/F

Bit clock output pin for AoUT
(DSP general output port -8)

Output

CMOS PORT

64

LRCKo(Po9)

Output 3I/F

L/R channel clock output pin
(DSP general output port -9)

Output

CMOS PORT

65

AiN(Pi4)

Input 3I/F

Audio data input for Audio DAC
(DSP general input port -4)

Input

Schmitt input

66

BCKi(Pi5)

Input 3I/F

Bit clock input pin for AiN
(DSP general input port -5)

Input

Schmitt input

67

LRCK(Pi6)

Input 3I/F

L/R channel clock for AiN
(DSP general input port -6)

Input

Schmitt input

68

VDD1

-

Power supply pin for 1.5V digital circuit.

-

69

VSS

-

Grounding pin for 1.5V digital circuit.

-

70

AWRC

Output 3AI/F

VCO control pin for active wide-range PLL.

Output

Applicable in CLV/CAV mode. 
Connect 0.033 uF.

71

PVDD3

-

Power supply pin for 3.3V CD PLL circuit.

-

72

PDo

Output 3AI/F

EFM and PLCK Phase difference signal output pin.

Output

4-state output ( PVDD3, 
Hiz,PVSS3,PVREF)

73

TMAXS

Output 3AI/F

TMAX detection result output pin.

Output

3-state output
(PVDD3,PVSS3,HiZ)

74

TMAX

Output 3AI/F

TMAX detection result output pin.

Output

3-state
output(PVDD3,PVSS3,HiZ)

75

LPFN

Input 3AI/F

PLL circuit LPF amplifier inversion input pin.

Input

Connect resister of LPF, refer 
to application circuit diagram.

76

LPFo

Output 3AI/F

PLL circuit LPF amplifier Output pin.

Output

Connect capacitor of LPF, refer 
to application circuit diagram.

77

PVREF

-

PLL circuit 1.65 V reference voltage pin.

-

Connected to VREF and VRO 
inside of IC. Connect 0.1uF.

78

VCoF

Output 3AI/F

VCO filter pin

Output

Connect 0.01uF.

79

PVSS3

-

Grounding pin for 3.3V CD PLL circuit.

-

80

SLCo

Output 3AI/F

EFM slice level output pin.
Output impedance =2.5k

Ω both of

analog/digital slice mode.

Output

Connect capacitor according 
with servo frequency band.

81

RFi

Input 3AI/F

RF signal input pin
Zin is selectable by command.

Input

Zin: 20k

Ω, 10kΩ,  5kΩ

82

RFRPi

Input 3AI/F

RF ripple signal input pin.

Input

-

83

RFEQo

Output 3AI/F

RF equalizer circuit output pin.

Output

Connect to RFRPI by 0.1uF, to 
RFI by 4700pF.

84

Vro

Output 3AI/F

1.65 V reference voltage output pin.

Output

Connected to VREF and 
PVREF inside of IC.
Connect 0.1uF+100uF.

85

RESiN

Output 3AI/F

Pin for connecting a resistor for reference current 
generation.

Output

Connect 22k//0.01uF.

86

VMDiR

Reference voltage output pin for LD APC.

Connect 0.1uF.

87

TESTR

Output 3AI/F

LPF connection pin for RFEQO offset correction 
circuit.

Output

Connect more than 0.015uF.

XL-UR27H

8 – 6

* 3A I/F : 3 V analog circuit input/output pin.

1.5 I/F : 1.5 V digital input/output pin.
3 I/F : 3 V digital input/output pin.

Note: The servo output pins (FOO, TRO, FMO, and DMO) become undefined or GND level under the following conditions:

• /RST pin = Low
• Crystal oscillation stopped according to the instructions by the Stop crystal oscillation command.
• Power supply for CD is OFF.
• SRAMSTB pin = High
To prevent the undefined pin states from affecting the servo circuitry or any other mechanical blocks in the system,
appropriate measures should be taken, such as using a driver IC supporting a standby feature to place the system in
standby mode while either of the above conditions is satisfied.

88

AGCi

Input 3AI/F

RF signal AGC amplifier input pin.

Input

89

Rfo

Output 3AI/F

RF signal generation amplifier output pin.

Output

90

RVDD3

-

Power supply for 3.3V RF amplifier core circuit.

91

LDo

Output 3AI/F

Laser diode amplifier output pin.

92

MDi

Input 3AI/F

Monitor photodiode amplifier input pin.

Input

Reference  Voltage=178mVtyp.

93

RVSS3

-

Grounding pin for RF amplifier core circuit.

94

FNi2

Input 3AI/F

Main beam signal input pin. To be connected to PIN 
diode C.

Input

95

FNi1

Input 3AI/F

Main beam signal input pin. To be connected to PIN 
diode A.

Input

96

FPi2

Input 3AI/F

Main beam signal input pin. To be connected to PIN 
diode D.

Input

97

FPi1

Input 3AI/F

Main beam signal input pin. To be connected to PIN 
diode B.

Input

98

TPi

Input 3AI/F

Sub beam signal input pin. To be connected to PIN 
diode F.

Input

99

TNPC

Output 3AI/F

TNI/TPI input common capacitor connection pin.

Output

Connect to VRO by capacitor.

100

TNi

Input 3AI/F

Sub beam signal input pin. To be connected to PIN 
diode E.

Input

XL-UR27H

8 – 7

1

NO USE

OUTPUT

CMOS INPUT / OUTPUT

OFF

Fix "L"

P96/ANEX1

2

NO USE

OUTPUT

CMOS INPUT / OUTPUT 

Fix "L"

P95/ANEX0

3

VOL_DATA

OUTPUT

CMOS INPUT / OUTPUT

COMMUNICATION WITH 
DATA OUTPUT

P94

4

VOL_CLK

OUTPUT 

CMOS INPUT / OUTPUT

OFF

COMMUNICATION WITH 
CLOCK OUTPUT

P93

5

NO  USE

OUTPUT 

CMOS INPUT / OUTPUT

Fix "L"

P92/TB2IN

6

NO  USE

OUTPUT 

CMOS INPUT / OUTPUT

Fix "L"

P91/TB1IN

7

VOL_LATCH

OUTPUT 

CMOS INPUT / OUTPUT

COMMUNICATION WITH 
LATCH OUTPUT

P90/TB0IN

8

BYTE

INPUT INPUT

-

EXTERNAL BUS. JOINT TO 
VSS IF NO USE

BYTE

9

CNVSS

INPUT INPUT

-

USED IN SINGLE MODE. 
CONNECT TO VSS 
THROUGH PULL DOWN 
RESISTOR. EXCLUSIVE USE 
FOR VCC DURING FLASH 
WRITING

CNVSS

10

XCIN

INPUT 

CMOS INPUT / OUTPUT

OFF

32.768kHz X'tal (SUB-CLOCK)

P87/XCIN

11

XCOUT

OUTPUT 

CMOS INPUT / OUTPUT

32.768kHz X'tal (SUB-CLOCK)

P86/XCOUT

12

RESET

INPUT INPUT

-

RESET INPUT. ACTIVE "L"
CONNECT TO WRITER 
RESET LINE DURING FLASH

RESET

13

X_OUT

OUTPUT CMOS 

OUTPUT

-

MICOM STANDARD
OSCILLATION OUTPUT
CONNECT TO 9.8MHz 
CERAMIC OSCILLATION

XOUT

14

GND

- 

-

-

CONNECT TO GND(VSS).

VSS

15

X_IN

INPUT CMOS 

INPUT

-

MICOM STANDARD
OSCILLATION OUTPUT
CONNECT TO 9.8MHz 
CERAMIC OSCILLATION

XIN

16

VCC

- -

-

SUPPLY INPUT TO MICOM 
(3.3V)
BACK-UP POWER SUPPLY

VCC1

17

NMI

INPUT

CMOS INPUT

-

CONNECT TO VCC 
THROUGH PULL UP RESIS-
TOR. (SET FOR FLASH)

P85/NMI

18

P-IN

INPUT

CMOS INPUT / OUTPUT

OFF

POWER FALURE DETEC-
TION. JUDGE AS POWER 
FAILURE IF FAIL TO DETECT 
EDGE WITHIN 90 msec.

P84/INT2

19

OSC

OUTPUT

CMOS INPUT / OUTPUT

OFF

OSCILLATOR FREQUENCY 
ADJUSTMENT. SET FOR 
H=415kHz, L=375kHz

P83/INT1

20

RX_IN

INPUT

CMOS INPUT / OUTPUT

REMOCON IN
(SHARP FORMAT)

P82/INT0

21

AMP DET

INPUT

CMOS INPUT / OUTPUT

POWER IC ABNORMAL 
DETECT ABNORMAL=L

P81

22

AMP MUTE

OUTPUT

CMOS INPUT / OUTPUT

AMP MUTE CONTROL L: 
MUTE OFF, H: MUTE ON

P80

23

AMP ON/OFF

OUTPUT

CMOS INPUT / OUTPUT

OFF

AMP ON/OFF CONTROL L: 
OPERATING MODE,
H: STANDBY MODE

P77

24

RDS_VOLT_CONT

OUTPUT

CMOS INPUT / OUTPUT

RDS FUNCTION CONTROL H: 
FM FUNC ONLY (H MODEL)

P76

25

RDS DATA

INPUT

CMOS INPUT / OUTPUT

RDS DATA in (H MODEL)

P75/TA2IN

XL-UR27H

8 – 8

26

RDS CLK

INPUT

CMOS INPUT / OUTPUT

OFF

RDS CLK (H MODEL)

P74/TA2OUT

27

IPOD_DETECT

INPUT

CMOS INPUT / OUTPUT

OFF

L:IPOD INSERT
H:W/O IPOD

P73/CTS2/RTS2/TA1IN

28

FLD RESET

OUTPUT

CMOS INPUT / OUTPUT

FL DRIVER RESET CONTROL

P72/CLK2/TA1OUT

29

IPOD_TXD

INPUT

Nch open

-

IPOD COMMUNICATION 
DATA IN (OPTION)

P71/RXD2/SCL2/TA0IN/TB5IN

30

IPOD_RXD

OUTPUT

Nch open

-

IPOD COMMUNICATION 
DATA IN (OPTION)

P70/TXD2/SDA2/TA0OUT

31

FLD DATA/FLASH_TXD

OUTPUT

CMOS INPUT / OUTPUT

OFF

COMMUNICATION WITH FL 
DRIVER 
( DATA OUT TO FLASH 
WRITER.)

P67/TXD1/SDA1

32

FLASH_RXD

OUTPUT

CMOS INPUT / OUTPUT

INPUT DATA FROM FLASH 
WRITER

P66/RXD1/SCL1

33

FLD SCK/FLASH_SCLK

OUTPUT

CMOS INPUT / OUTPUT

COMMUNICATION WITH 
FL_DRIVE. CLOCK OUTPUT
( INPUT CLOCK  FROM 
FLASH WRITER. )

P65/CLK1

34

FLD CS/FLASH_BUSY

OUTPUT

CMOS INPUT / OUTPUT

COMMUNICATION WITH 
FL_DRIVER. Chip Select
( BUSY OUTPUT TO FLASH 
WRITER. BUSY: "H")

P64/CTS1/RTS1/CTS0/CLKS1

35

NO USE

OUTPUT

CMOS INPUT / OUTPUT

OFF

Fix "L"

P63/TXD0/SDA0

36

NO USE

OUTPUT

CMOS INPUT / OUTPUT

Fix "L"

P62/RXD0/SCL0

37

NO USE

OUTPUT

CMOS INPUT / OUTPUT

Fix "L"

P61/CLK0

38

CP_SCL

OUTPUT

CMOS INPUT / OUTPUT

IPOD CO-PROCESSOR I2C 
COMMUNICATION CLOCK

P60/CTS0/RTS0

39

CP_SDA

INPUT /

OUTPUT

CMOS INPUT / OUTPUT

OFF

IPOD CO-PROCESSOR I2C 
COMMUNICATION DATA

P57/CLKOUT

40

CP_nRESET

OUTPUT

CMOS INPUT / OUTPUT

SUMMER TIME SWITCH
OUTPUT 
L:NORMAL      H:+1HOUR

P56

41

FLASH_EPM

INPUT

CMOS INPUT / OUTPUT

CONNECT TO  VSS 
THROUGH PULL DOWN
(SET FLASH WRITING) 

P55

42

NO USE

OUTPUT

CMOS INPUT / OUTPUT

Fix "L" 

P54

43

NO USE

OUTPUT

CMOS INPUT / OUTPUT

OFF 

Fix "L" 

P53

44

NO USE

OUTPUT

CMOS INPUT / OUTPUT

Fix "L" 

P52

45

NO USE

OUTPUT

CMOS INPUT / OUTPUT

Fix "L" 

P51

46

FLASH CE

INPUT

CMOS INPUT / OUTPUT

FLASH CHIP ENABLE 

P50

47

NO USE

OUTPUT

CMOS INPUT / OUTPUT

OFF 

Fix "L" 

P47

48

NO USE

OUTPUT

CMOS INPUT / OUTPUT

Fix "L" 

P46

49

NO USE

OUTPUT

CMOS INPUT / OUTPUT

Fix "L" 

P45

50

NO USE

OUTPUT

CMOS INPUT / OUTPUT

Fix "L" 

P44