Sharp XL-60 (serv.man20) Service Manual ▷ View online
– 47 –
XL-60H/70H
IC801 VHiTA2109F/-1:Servo Pre Amp. (TA2109F)
1
VCC
—
Power voltage terminal
2
FNI
Input
Main beam amp input terminal
3
FPI
Input
Main beam amp input terminal
4
TPI
Input
Sub-beam amp input terminal
5
TNI
Input
Sub-beam amp input terminal
6
MDI
Input
Monitor photodiode amp input terminal
7
LDO
Output
Laser diode amp output terminal
8
SEL
Input
Laser diode control signal input and APC circuit ON/OFF signal input terminal
9
TEB
Input
Tracking error balance adjustment signal input terminal
To be controlled by 3-value PWM signal. (PWM carrier = 88.2 kHz)
To be controlled by 3-value PWM signal. (PWM carrier = 88.2 kHz)
10
2VRO
Output
Standard voltage (2VR) output terminal. When Vcc = 5V, 2VR = 4.2V.
11
TEN
Input
Tracking error signal generation amp reversed phase input terminal
12
TEO
Output
Tracking error signal generation amp output terminal
13
SBAD
Output
Sub-beam addition signal output terminal
14
FEO
Output
Focus error signal generation amp output terminal
15
FEN
Input
Focus error signal generation amp reversed phase input terminal
16
VRO
Output
Standard voltage (VR) output terminal. When Vcc = 5V, VR = 2.1V.
17
RFRP
Output
Track count signal generation amp output terminal
18
RFIS
Input
RFRP detection circuit input terminal
19
RFGO
Output
RF signal output terminal
20
RFGC
Input
RF amplitude adjustment control signal input terminal
The amplitude of RF signal can be controlled by using the 3-value PWM signal (PWM
carrier = 88.2 kHz) which is output from the RFGC terminal of TC9432F.
The amplitude of RF signal can be controlled by using the 3-value PWM signal (PWM
carrier = 88.2 kHz) which is output from the RFGC terminal of TC9432F.
21
AGCI
Input
RF signal amplitude adjustment amp input terminal
22
RFO
Output
RF signal generation amp output terminal
23
GND
—
GND terminal
24
RFN
Input
RF reversed phase input terminal
Terminal Name
Pin No.
Input/Output
Function
IC801 VHiTA2109F/-1:Servo Pre Amp. (TA2109F)
Figure 47 BLOCK DIAGRAM OF IC
15k
Ω
15k
Ω
50k
Ω
10k
Ω
7.96k
Ω
10k
Ω
21k
Ω
21k
Ω
12k
Ω
12k
Ω
20k
Ω
20k
Ω
23.5k
Ω
12k
Ω
1.53k
Ω
20k
Ω
3.3k
Ω
180k
Ω
60k
Ω
60k
Ω
20k
Ω
20k
Ω
20k
Ω
180k
Ω
180k
Ω
180k
Ω
13k
Ω
2.12k
Ω
680k
Ω
1k
Ω
47k
Ω
1.74k
Ω
24k
Ω
30k
Ω
24k
Ω
21k
Ω
29k
Ω
10k
Ω
7.67k
Ω
30k
Ω
10k
Ω
10k
Ω
20k
Ω
3.3k
Ω
20pF
20pF
40pF
20pF
40pF
36pF
10pF
PEAK
BOTTOM
re = 130
Ω
SW
3
SW
2
SW
1
65
µ
A
50
µ
A
20
µ
A
2
3
4
5
1
7
8
9
6
12
13
14
15
11
17
18
19
10
16
22
23
24
21
20
VCC
FNI
FPI
TPI
TNI
MDI
LDO
SEL
TEB
2VRO
TEN
TEO
RFN
GND
RFO
AGCI
RFGC
RFGO
RFIS
RFRP
VRO
FEN
FEO
SBAD
3 STATE
DET.
I . I
I . I
SEL
L
HiZ
H
SW1
SW2
LDC
SW3
ON
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
LDC
XL-60H/70H
– 48 –
IC802 VHiTC9462F/-1: Servo/Signal Control (TC9462F) (1/3)
1*
TEST0
Input
Test mode terminal. To be opened usually.
2*
/HSO
Output
Playback speed mode flag output terminal.
3*
/UHSO
Output
4*
EMPH
Output
Sub-code Q data emphasis flag output terminal. "H": Emphasis ON "L": Emphasis OFF
The output polarity can be inverted by command.
The output polarity can be inverted by command.
5*
LRCK
Output
Channel clock (44.1 kHz) output terminal. "L": L channel "H": R channel
The output polarity can be inverted by command.
The output polarity can be inverted by command.
6
VSS
—
Digital ground terminal.
7*
BCK
Output
Bit clock (1.4122 MHz) output terminal.
8*
AOUT
Output
Audio data output terminal.
9
DOUT
Output
Digital out output terminal.
10*
MBOV
Output
Buffer memory over signal output terminal. "H": Over
11*
IPF
Output
Correction flag output terminal.
"H": When AOUT output is correction-disabled symbol in case of C2 correction output.
"H": When AOUT output is correction-disabled symbol in case of C2 correction output.
12*
SBOK
Output
Sub-code Q data CRCC judgment result output terminal. "H": When judgment result is OK.
13*
CLCK
Input/Output
Sub-code P-W data read clock output/input terminal. Selectable with command bit.
14
VDD
—
Digital + power terminal.
15
VSS
—
Digital ground terminal.
16*
DATA
Output
Sub-code P-W data output terminal.
17*
SFSY
Output
Playback system frame sync signal output terminal.
18*
SBSY
Output
Sub-code block sync output terminal. "H": On S1 position when the sub-code sync is detected.
19*
SPCK
Output
Processor status signal read clock (176.4 kHz) output terminal.
20*
SPDA
Output
Processor status signal output terminal.
21*
COFS
Output
Correction system frame clock (7.35 kHz) output terminal.
22*
MONIT
Output
LSI internal signal monitor terminal.
It is possible to monitor the DSP internal flag and PLL system clock with the microcomputer
command. Terminal for serial output of text data according to command .
It is possible to monitor the DSP internal flag and PLL system clock with the microcomputer
command. Terminal for serial output of text data according to command .
23
VDD
—
Digital + power terminal.
24
TESIO0
Input
Test input/output terminal. To be fixed to "L" usually.
Terminal to input the text data read clock according to command.
Terminal to input the text data read clock according to command.
25
P2VREF
—
2VREF terminal for PLL system.
26*
HSSW
Output
VREF voltage in case of x2 speed/x4 speed.
27*
ZDET
Output
1-bit DAC zero detection flag output terminal.
28
PDO
Output
Terminal to output the phase difference between EFM signal and PLCK signal.
29*
TMAXS
Output
TMAX detection result output terminal. To be selected with command bit TMPS.
30
TMAX
Output
TMAX detection result output terminal. To be selected with command bit TMPS.
31
LPFN
Input
Low-pass filter amp inverted input terminal.
32
LPFO
Output
Low-pass filter amp output terminal.
33
PVREF
—
VREF terminal for PLL system.
34
VCOREF
Input
VCO center frequency standard level terminal. To be fixed to PVref usually.
35
VCOF
Output
VCO filter terminal.
36
AVSS
—
Analog system ground terminal.
37
SLCO
Output
Data slice level generation DAC output terminal.
38
RFI
Input
RF signal input terminal.
Pin No.
Port Name
Function
Input/Output
H
H
x1 speed playback
H
L
x2 speed playback
L
H
x4 speed playback
L
L
—
/UHSO
/HSO
Playback speed
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Longer than specific period
"P2VREF"
Shorter than specific period
"VSS"
Within specific period
"HIZ"
TMAX detection result
TMAX output
– 49 –
XL-60H/70H
39
AVDD
—
Analog system power terminal.
40
RFCT
Input
RFRP signal center level input terminal.
41
RFZI
Input
RFRP zero cross input terminal.
42
RFIP
Input
RF ripple signal input terminal.
43
FEI
Input
Focus error signal input terminal.
44
SBAD
Input
Sub-beam addition signal input terminal.
45
TSIN
Input
Test input terminal. To be fixed to Vref usually.
46
TEI
Input
Tacking error input terminal. (Tracking servo ON: Taking-in).
47
TEZI
Input
Tracking error, zero cross input termina.l
48
FOO
Output
Focus equalizer output terminal.
49
TRO
Output
Tracking equalizer output terminal.
50
VREF
—
Analog standard power terminal.
51
RFGC
Output
RF amplitude adjustment control signal output terminal.
3-value PWM signal is output. (PWM carrier = 88.2 kHz)
3-value PWM signal is output. (PWM carrier = 88.2 kHz)
52
TEBC
Output
Tracking balance control signal output terminal.
3-value PWM signal is output. (PWM carrier = 88.2 kHz)
3-value PWM signal is output. (PWM carrier = 88.2 kHz)
53
FMO
Output
Feed equalizer output terminal. 3-value PWM signal is output. (PWM carrier = 88.2 kHz)
54*
FVO
Output
Speed error signal or feed search EQ output terminal.
3-value PWM signal is output. (PWM carrier = 88.2 kHz)
3-value PWM signal is output. (PWM carrier = 88.2 kHz)
55
DMO
Output
Disc equalizer output terminal.
3-value PWM signal is output. (PWM carrier = DSP system 88.2 kHz, sync with PXO)
3-value PWM signal is output. (PWM carrier = DSP system 88.2 kHz, sync with PXO)
56
2VREF
—
Analog standard power terminal (2xVREF)
57
SEL
Output
APC circuit ON/OFF signal output terminal.
When laser is ON and UHS = L, "Hi-Z". When UHS = H, "H" output is obtained.
When laser is ON and UHS = L, "Hi-Z". When UHS = H, "H" output is obtained.
58*
FLGA
Output
Internal signal monitor external flag output terminal.
TEZC, FOON, FOK and RFZC signals can be selected with command.
TEZC, FOON, FOK and RFZC signals can be selected with command.
59*
FLGB
Output
Internal signal monitor external flag output terminal.
DFCT, FOON, FMON and RFZC signals can be selected with command.
DFCT, FOON, FMON and RFZC signals can be selected with command.
60*
FLGC
Output
Internal signal monitor external flag output terminal.
TRON, TRSR, FOK, and SRCH signals can be selected with command.
TRON, TRSR, FOK, and SRCH signals can be selected with command.
61*
FLGD
Output
Internal signal monitor external flag output terminal.
TRON, DMON, HYS and SHC signals can be selected with command.
TRON, DMON, HYS and SHC signals can be selected with command.
62
VDD
—
Digital + power terminal.
63
VSS
—
Digital ground terminal.
64*
IO0
Input/Output
General-use I/O port.
65*
IO1
The input port and output port can be selected with command. In case of input port the terminal
66*
IO2
state (H/L) can be read with the read command.
67*
IO3
In case of output port the terminal state (H/L/HiZ) can be controlled with command.
68*
/DMOUT
Input
Terminal to set the mode to output 2-value PWM of feed equalizer from IO0,1 terminal and 2-
value PWM of disc equalizer from IO2,3 terminal. "L" active
value PWM of disc equalizer from IO2,3 terminal. "L" active
69*
/CKSE
Input
To be opened usually.
70*
/DACT
Input
DAC test mode terminal. To be opened usually.
71
TESIN
Input
Test input terminal (externally provided VCO clock input terminal). To be fixed to "L" usually.
72
TESIO1
Input
Test input/output terminal. To be fixed to "L" usually.
73
VSS
—
Digital ground terminal.
74
PXI
Input
DSP system clock oscillation circuit input terminal. To be fixed to "L" usually.
75*
PXO
Output
DSP system clock oscillation circuit output terminal.
76
VDD
—
Digital + power terminal.
77
XVSS
—
System clock oscillation circuit ground terminal.
78
XI
Input
System clock oscillation input terminal.
79
XO
Output
System clock oscillation circuit output terminal.
80
XVDD
—
System clock oscillation circuit + power terminal.
81
DVSR
—
R channel D/A converting section power terminal.
82
RO
Output
R channel data forward rotation output terminal.
IC802 VHiTC9462F/-1: Servo/Signal Control (TC9462F) (2/3)
Pin No.
Port Name
Function
Input/Output
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
XL-60H/70H
– 50 –
83
DVDD
—
D/A converting section power terminal.
84
DVR
—
Reference voltage terminal.
85
LO
Output
L channel data forward rotation output terminal.
86
DVSL
—
L channel D/A converting section power terminal.
87*
TEST1
Input
Test mode terminal. To be opened usually.
88*
TEST2
Input
Test mode terminal. To be opened usually.
89*
TEST3
Input
Test mode terminal. To be opened usually.
90-93
BUS0-BUS3
Input/Output
Microcomputer interface data input/output terminal.
94
VDD
—
Digital + power terminal.
95
VSS
—
Digital ground terminal.
96
BUCK
Input
Microcomputer interface clock input terminal.
97
/CCE
Input
Microcomputer interface chip enable signal input terminal. "L": BUS0 to 3 is active.
98*
TEST4
Input
Test mode termina. To be opened usually.
99*
/TSMOD
Input
Local test mode selection terminal.
100
/RST
Input
Reset signal input terminal. "L": Reset.
IC802 VHiTC9462F/-1: Servo/Signal Control (TC9462F) (3/3)
Pin No.
Port Name
Function
Input/Output
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Figure 50 BLOCK DIAGRAM OF IC
IC802 VHiTC9462F/-1: Servo/Signal Control (TC9462F)
2
3
4
5
1
7
8
9
6
12
13
14
15
11
17
18
19
10
16
22
23
24
25
21
27
28
29
20
30
26
42
43
44
45
41
47
48
49
50
46
32
33
34
35
31
37
38
39
40
36
89
88
87
86
90
84
83
82
81
85
99
98
97
96
100
94
93
92
91
95
72
73
74
75
71
77
78
79
70
80
76
62
63
64
65
61
67
68
69
60
66
52
53
54
55
51
57
58
59
56
LPF
1Bit
DAC
Microcomputer
interface
Correction
circuit
Audio output
circuit
Digital
out
16KRAM
Sub-code
demodulation
circuit
Status
PLL
TMAX
VCO
Data
slicer
CLV
servo
D/A
PWM
Servo control
ROM
RAM
Digital equalizer
adjustment circuit
Address
circuit
Clock
generator
/RST
/TSMOD
TEST4
/CCE
BUCK
VSS
VDD
BUS3
BUS2
BUS1
BUS0
TEST3
TEST2
TEST1
DVSL
LO
DVR
DVDD
RO
DVSR
LPFN
LPFO
PVREF
VCOREF
VCOF
AVSS
SLCO
RFI
AVDD
RFCT
RFZI
RFRP
FEI
SBAD
TSIN
TEI
TEZI
FOO
TRO
VREF
TMAX
TMAXS
PDO
ZDET
HSSW
P2VREF
TESIO0
VDD
MONIT
COFS
SPDA
SPCK
SBSY
SFSY
DATA
VSS
VDD
CLCK
SBOK
IPF
MBOV
DOUT
AOUT
BCK
VSS
LRCK
EMPH
/UHSO
/HSO
TEST0
RFGC
TEBC
FMO
FVO
DMO
2VREF
SEL
FLGA
FLGB
FLGC
FLGD
VDD
VSS
IO0
IO1
IO2
IO3
/DMOUT
/CKSE
/DACT
TESIN
TESIO1
VSS
PXI
PXO
VDD
XVSS
XI
XO
XVDD
Synchronizing
signal guarantee
EFM demodulation
A/D
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