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– 41 –

• Outline
The TDA1307 is an advanced oversampling digital filter employing bitstream conversion technology, which has been designed
for use in premium performance digital audio applications. Audio data is input to the TDA1307 through its multiple-format interface.
Any of the four formats (IIS, Sony 16, 18 or 20-bit) are acceptable. By using a highly accurate audio data processing structure,
including 8 times oversampling digital filtering and up to 4th order noise shaping, a high quality bitstream is produced which, when
used in the recommended combination with the TDA1547 bitstream DAC, provides the optimum in dynamic range and signal-to-
noise performance. With the TDA1307, a high degree of versatility is achieved by a multitude of functional features and their easy
accessibility; error concealment functions, audio peak data information and an advanced patented digital fade function are
accessible through a simple microprocessor command interface, which also provides access to various integrated system settings
and functions.

1

WS

Input

Word select input to data interface

2

SCK

Input

Clock input to data interface

3

SD

Input

Data input to interface

4

EFAB

Input (Note 1)

Error flag: (active HIGH) input from decoder chip indicating unreliable data

5

SBCL

Input

Subcode clock: a 10-bit burst clock (typ. 2.8224 MHz) input which synchronizes the subcode data

6

SBDA

Input

Subcode data: a 10-bit burst of data, including flags and sync bits, serially input once per
frame, clocked by burst clock input SBCL

7*

CDEC

Output

Decoder clock output: frequency division programmable by means of pins 14 (CLC1) and 17
(CLC2) to output 192, 256, 384 or 768 times fs

8

VDD3

—

Positive supply 3

9

VSS2

—

Ground 2

10*

DOBM

Output

Digital audio output: this output contains digital audio samples which have received
interpolation, attenuation and muting plus subcode data. Transmission is in biphase-mark
code.

11*

DSL

Output

Digital silence detected (active LOW) on left channel

12*

DSR

Output

Digital silence detected (active LOW) on right channel

13

DSTB

Input (Note 2)

DOBM stand-by mode enforce pin (active HIGH)

14

CLC1

Input

Application mode programming pin for CDEC (pin 7) frequency division

15*

CMIC

Output

Clock output, provided to be used as running clock by microprocessor (in master mode only),
output 96fs

16

VSS3

—

Ground 3

17

CLC2

Input

Application mode programming pin for CDEC (pin 7) frequency division

18

CDCC

Input

Master/Slave mode selection pin

19*

RESYNC

Output

Resynchronization: out-of-lock indication from data input section (active HIGH)

20

POR

Input (Note 2)

Power-on reset (active LOW)

21

VDD1

—

Supply voltage 1

22

XTAL1

Input

Crystal oscillator terminal: local crystal oscillator sense

23

XTAL2

Output

Crystal oscillator output: drive output to crystal or forced input in slave mode

24

VDDOSC

—

Positive supply connection to crystal oscillator circuitry

25

VSSOSC

—

Ground connection to crystal oscillator circuitry

26*

MODE

Input (Note 2)

Evaluation mode programming pin (active LOW); in normal operation, this pin should be left
open-circuit or connected to the positive supply

27

DOL

Output

Data output left channel to bitstream DAC TDA1547

28*

NDOL

Output

Complementary data output left channel to TDA1547

29

VDDAL

—

Positive supply connection to output data driving circuitry, left channel

30

VSSAL

—

Ground connection to output data driving circuitry, left channel

31

VSSAR

—

Ground connection to output data driving circuitry, right channel

32

VDDAR

—

Positive supply connection to output data driving circuitry, right channel

33

DOR

Output

Data output right channel to TDA1547

34*

NDOR

Output

Complementary data output right channel to TDA1547

35

CDAC

Output

Clock output to bitstream DAC TDA1547

36, 37

TEST1, TEST2

Input (Note 1)

Test mode input. In normal operation this pin should be connected to ground

38

DA

Input/Output

Bidirectional data line intended for control data from the microprocessor and peak data from

(Note 2)

the TDA1307

In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.

– 42 –

39

CL

Input (Note 2)

Clock input, to be generated by the microprocessor

40

Vss

1

—

Ground 1

41

VDD3

—

Supply voltage 2

42

RAB

Input (Note 2)

Command/peak data request line

1fs AUDIO DATA INPUTS

WS

SCK

SD

EFAB

1

2

3

4

TDA1307

MULTIPLE FORMAT

INPUT INTERFACE

ERROR CONCELMENT,

INTERPOLATION, MUTING

DIGITAL

OUTPUT

DIGITAL SILENCE DETECTION

DEEMPHASIS FILTER

FIR HALFBAND FILTER

STAGE  1: 1fs to 2fs

DC-CANCELING FILTER

PEAK DETECTION

FADE FUNCTION

VOLUME CONTROL

FIR HALFBAND FILTER

STAGE 2: 2 fs to 4 fs

FIR HALFBAND FILTER

STAGE 3: 4 fs to 8 fs

DITHER AND SCALING

3rd/4th ORDER

NOISE SHAPER

27

28

35

34

33

26

DOL

NDOL CDAC NDOR DOR

MODE

BITSTREAM DATA OUTPUTS

MICROPROCESSOR INTERFACE

DA  38

CL  39

RAB  42

POR  20

VDD3  8

VDD1  21

VDDOSC  24

VDDAL  29

VDDAR  32

VDD2  41

DSR  12

DSL  11

TEST1  36

TEST2  37

19  RESYNC

10  DOBM
13  DSTB

5  SBCL
6  SBDA

CRYSTAL

OSCIL-
LATOR

25  VSSOSC

22  XTAL1

23  XTAL2

15  CMIC

7  CDEC

14  CLC1

17  CLC2

18  CDCC

9  VSS2

16  VSS3

30  VSSAL

31  VSSAR

40  VSS1

CLOCK GENERATION & DISTRIBUTION

WS

SCK

SD

EFAB

SBCL

SBDA

CDEC

VDDC3

VSSC2

DOBM

DSL

DSR

DSTB

CLC1

CMIC

VSSC3

CLC2

CDCC

RESYNC

POR

VDDC1

RAB

VDDC2

VSSC1

CL

DA

TEST2

TEST1

CDAC

NDOR

DOR

VDDAR

VSSAR

VSSAL

VDDAL

NDOL

DOL

MODE

VSSOSC

VDDOSC

XTAL2

XTAL1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

TDA1307

Notes
1. These pins are configured as internal pull-down.
2. These pins are configured as internal pull-up.

– 43 –

• Outline
It is the low power consuming CMOSIC which has the latch in the 8-bit shift register and can asynchronously latch the data latched
in the shift register. Since the output (O1 to O8) is the open drain output (Since the protective diode is not provided, the voltage
of VDD or more to max. 7V is applicable, and the drive is possible at 36mA per output up to the total output of 150mA. (Static
operation mode)

1

SIN

Input

Serial data input terminal

2

CK

Input

Shift clock of shift register

3

LATCH

Input

When the terminal is turned to "L", the latch output is held.
Moreover, the latch output also varies as the shift register output varies when it is "H".

4*

SOUT

Output

Output of shift register of the final step

5

EN

Input

Enable terminal of O1 to O8
When the terminal is "L", the latch output appears as it is.
However, the output Qn is "L" when the latch output is "H", and Qn is "hi-Z" when the latch
output is "L".

6

RST

Input

Shift register, latch reset

7 - 9

GND

—

0V   Power supply

10

O8

Output

Latch output at 8th step of shift register

11

O7

Output

Latch output at 7th step of shift register

12

O6

Output

Latch output at 6th step of shift register

13

O5

Output

Latch output at 5th step of shift register

14

O4

Output

Latch output at 4th step of shift register

15

O3

Output

Latch output at 3rd step of shift register

16

O2

Output

Latch output at 2nd step of shift register

17

O1

Output

Latch output at 1st step of shift register

18

VDD

—

+VDD power supply

In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Note) Output of O1 to O8 is an open-drain type, and when the output of the shift register is "H", the output becomes the level "L".

SIN

CK

LATCH

SOUT

EN

RST

GND

GND

GND

V

DD

01

02

03

04

05

06

07

08

– 44 –

1

LED3, P83

DATA_IN

Input

External IC communication input

2

LED2, P82

DATA_OUT

Output

External IC communication output

3

LED1, P81

IC_CLK

Input

External IC communication clock

4

LED0, P80

—

Input

Not used

5

AN0, PA0

KEY

Input

Key input. A/D input. VER.1

6

AN1, PA1

VOL DIS

Input

A/D input to display VOL value

7

AN2, PA2

KEYA

Input

Key input. A/D input. VER.2

8

AN3, PA3

KEYB

Input

Key input. A/D input. VER.2

9

AN4, PA4

KEYC

Input

Key input. A/D input. VER.2

10-12

AN5, PA5-AN7, PA7

—

Input

Not used

13

VDD

VDD

—

Power supply

14

OSC2

OSC2

Output

Oscillator

15

OSC1

OSC1

Input

Oscillator

16

VSS

VSS

—

Power supply

17*

NC

—

—

Not used

18

TXD, SBD0, P00

SDATA

Output

Output to serial/parallel converter for LED display. Data output

19

RXD, SBI0, P01

SLATCH

Output

Output to serial/parallel converter for LED display. Latch output

20

SBT0, P02

SCLK

Output

Output to serial/parallel converter for LED display. Clock output

21

BUZZER, P06

IC_RESET

Output

Reset output to external IC

22*

RMOUT, P10

AMUTE

Output

Output for AUDIO MUTE

23*

P11

CL_CONT

Output

Clock control between external IC and IC

24

P12, TMIO2

DCLK

Output

Setting output to D/A. Clock output

25

P13, TMIO3

DLATCH

Output

Setting output to D/A. Latch output

26

P14, TMIO4

DDATA

Input/Output Setting output to D/A. Data input/output

27

P20, IRQ0

PROTECT

Input

PROTECT signal detection input

28

P21, IRQ1, SENS

P-IN

Input

Warning input

29

P22, IRQ2

IC_STB

Input

External IC communication strobe

30

P60

DIG_B

Output

Digital input switch B
Switch of digital input is controlled with DIG_A and B.

31

P61

DIG_A

Output

Digital input switch A

32

P62

MUTE

Output

Output for digital mute

33

P63

AUX3

Output

Input relay of AUX3 is switched.

34

P64

AUX2

Output

Input relay of AUX2 is switched.

35

P65

AUX1

Output

Input relay of AUX1 is switched.

36

P66

AMP DIG

Output

Input (digital, analog) to AMP is switched.

37*

P67

AMP ANA

Output

Input (digital, analog) to AMP is switched.

38

P70

DIG_C

Output

Digital input switch C
Switch of digital input accompanied to AUX1 is controlled.

39

P27, NRST

RESET

Input

Reset

40

MMOD

TEST

—

TEST

41

P87, LED7

SP_RLY

Output

ON/OFF of speaker relay

42

P86, LED6

POWER

Output

Control terminal of power supply

43

P85, LED5

MUTE

Output

Line mute for recording

44

P84, LED4

YOBI OUT

Output

Warning output

In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.