Sharp SM-SX1 (serv.man2) Service Manual ▷ View online
SM-SX1H
– 37 –
IC800 VHiYM3436D/-1: Digital Interface Receiver (YM3436D)
1
DAUX
Input
Audio data auxiliary input
2*
HDLT
Output
Asynchronous buffer operation flag output
3
DOUT
Output
Audio data output
4*
VFL
Output
Validity flag output
5*
OPT
Output
Synchronous signal output (fs) for DAC
6*
SYNC
Output
Synchronous signal output (fs) for DSP
7
MCC
Output
Bit clock output (64fs)
8
WC
Output
Word clock output (fs)
9*
MCB
Output
Bit clock output (128fs)
10
MCA
Output
Bit clock output (256fs)
11
SKSY
Input
Clock synchronizing control input
12
XI
Input
Quartz oscillator connection, or external clock input (256fs)
13
XO
Output
Quartz oscillator connection
14*
P256
Output
VCO clock output (When clocked, 256fs)
15
LOCKN
Output
PLL lock flag output ('L': Clocked, 'H': Unlocked)
16
VSS
—
Grand (logic system)
17*
TST2
Output
LSI test terminal (As usual, don't connect it.)
18
DIM1
Input
Data input mode selection 1
19
DIM0
Input
Data input mode selection 0
20
DOM1
Input
Data output mode selection 1
21
DOM0
Input
Data output mode selection 0
22
KM1
Input
Clock mode selection 1 ('H': PLL auto switch, 'L': XI fixed)
23
RSTN
Input
System reset input (active low)
24
VDDA
—
+5V power supply (VCO system. Externally connect it to VDD.)
25
CTLN
Input
VCO control input
26
PCO
Output
PLL phase comparative output
27*
N.C.
—
Not used
28
CTLP
Input
VCO adjustment input (As usual, connect it to VSSA.)
29
VSSA
—
Grand (VCO system. Externally connect it to VSS.)
30*
TSTN
Input
LSI test terminal (As usual, it is not connected.)
31
KM2
Input
Clock mode selection 2 ('H": PLL synchronization, 'L': XI synchronization)
32
KM0
Input
Clock mode selection 0 ('H': EXTW input, 'L': DDIN input)
33
FS1
Output
Sampling frequency code output 1/channel status output
34
FS0
Output
Sampling frequency code output 0/user data output
35
CSM
Input
Channel status, user data output method selection
36
EXTW
Input
External synchronizing auxiliary input, Word clock
37
DDIN
Input
EIAJ(AES/EBU) digital audio interface signal input
38*
LR
Output
PLL word clock output (When locked, fs)
39
VDD
—
+5V power (logic system)
40
ERR
Output
Data error flag output
41
EMP
Output
Emphasis control code output/block start synchronizing signal output
42*
CDO
Output
Microcomputer interface data output
43
CCK
Input
Microcomputer interface clock input
44
CLD
Input
Microcomputer interface load input
Pin No.
Port Name
Input/Output
FUNCTION TABLE OF IC
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
• Outline
YM3436D(DIR2) is a LSI which receives and demodulate the digital/audio/interface/format signals which comply with EIAJ CP-
340 and AES/EBU. Keeping the features of the existing YM3623B(DIR), it is designed to not only strengthen the external
synchronization, error process and other functions but also be more general for the channel status, user data output and other
general applications.
YM3436D(DIR2) is a LSI which receives and demodulate the digital/audio/interface/format signals which comply with EIAJ CP-
340 and AES/EBU. Keeping the features of the existing YM3623B(DIR), it is designed to not only strengthen the external
synchronization, error process and other functions but also be more general for the channel status, user data output and other
general applications.
Function
SM-SX1H
– 38 –
Figure 38 BLOCK DIAGRAM OF IC
SEL
PLL
EIAJ(AES/EBU)
Digital Audio
Interface Decoder
Microcomputer Interface
Data Clock
Control
S/P
P/S
Asynchronous
Buffer
(1 word per
each of
L and R)
System Clock
Timing Generator
EXTW
DDIN
CSM
ERR
EMP
EMP
FS1,0
CCK,CLD
CDO
DAUX
DIM1,0
HDLT
DOM1,0
DOUT
VFL
TST2
TSTN
RSTN
MCA,MCB,MCC,
WC,SYNC,OPT
KM0
VDDA
VSSA
PCO
CTLP,CTLN
LR
LOCKN
P256
KM2
XI
XO
KM1
SKSY
VDD
VSS
36
37
35
40
41
41
43 44
42
1
18 19
2
20 21
3
4
17
30
23
5
10
~
16
39
11
22
13
12
31
14
15
38
25 28
26
29
24
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
33
32
31
30
29
28
27
26
25
24
23
44
43
42
41
40
39
38
37
36
35
34
DAUX
HDLT
DOUT
VFL
OPT
SYNC
MCC
WC
MCB
MCA
SKSY
XI
XO
P256
LOCKN
VSS
TST2
DIM1
DIM0
DOM1
DOM0
KM1
FS1
KM0
KM2
TSTN
VSSA
CTLP
(NC)
PCO
CTLN
VDDA
RSTN
CLD
CCK
CDO
EMP
ERR
VDD
LR
DDIN
EXTW
CSM
FS0
IC800 VHiYM3436D/-1: Digital Interface Receiver (YM3436D)
SM-SX1H
– 39 –
1, 2
DI
Input with pull-up resistor
Input data
3, 4
BCKI
Input with pull-up resistor
Bit clock on the input side
5
LRCI
Input with pull-up resistor
Word clock on the input side
6
ICLK
Input
System clock input on the input side
7
ICKSL
Input with pull-up resistor
System clock on the input side (ICLK) selection. H:384fsi, L: 256fsi
Input format setting at IFM1 and IFM2
8*, 9*
IFM1
Input with pull-up resistor
10, 11
IFM2
Input with pull-up resistor
12, 13
VDD
—
Power supply terminal (5V)
14, 15
DMUTE
Input with pull-up resistor
(Direct) mute
16
MCOM
Input with pull-up resistor
Function switch of 17 to 20 pins
17
MDT/FSI1
Input with pull-up resistor
In case of MCOM=H, Microcomputer data input: MDT
In case of MCOM=L, De-emphasis frequency setting: FSI1
In case of MCOM=L, De-emphasis frequency setting: FSI1
In case of MCOM=H, Bit-clock for microcomputer data input: MCK
In case of MCOM=L, De-emphasis frequency setting :FSI2
In case of MCOM=L, De-emphasis frequency setting :FSI2
Input sample frequency setting (for de-emphasis)
18
MCK/FSI2
Input with pull-up resistor
19, 20
MLEN/DEEM
Input with pull-up resistor
In case of MCOM=H, Microcomputer data word latch clock: MLEN
In case of MCOM=L, De-emphasis ON/OFF control: DEEM
In case of MCOM=L, De-emphasis ON/OFF control: DEEM
Output format setting with OW18N, OW20N
Time of IISN=H (normal mode)
21, 22
OW18N
Input with pull-up resistor
Time of IISN=L (IIS mode)
23, 24
OW20N
Input with pull-up resistor
25, 26
IISN
Input with pull-up resistor
IIS output mode selection. H: Normal mode, L: IIS mode
27*
STATE
Output
Output to express the internal operational state (for operation check)
28*
TST1N
Input with pull-up resistor
Control of output dither. H: Dither OFF, L: Dither ON
29*
TST2N
Input with pull-up resistor
Test terminal. Set at H.
30, 31
RSTN
Input with pull-up resistor
Reset terminal
32, 33
VSS
—
GND terminal (0V)
IC801 VHiSM5844AF-1: Sampling Rate Converter (SM5844AF) (1/2)
Pin No.
Port Name
Input/Output
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
• Outline
SM5844AF is a special LSI for sampling rate converter, having a function to asynchronously covert the sample rate of the digital
audio signal. The input/output interface correspond to the input data of 16/20-bit word length and the output data of 16/18/20-bit
word length. Moreover, it integrates the digital de-emphasis filter, digital attenuator and other functions.
The package is a 44-pin QFP type, and the LSI is excellent in the cost performance.
SM5844AF is a special LSI for sampling rate converter, having a function to asynchronously covert the sample rate of the digital
audio signal. The input/output interface correspond to the input data of 16/20-bit word length and the output data of 16/18/20-bit
word length. Moreover, it integrates the digital de-emphasis filter, digital attenuator and other functions.
The package is a 44-pin QFP type, and the LSI is excellent in the cost performance.
Function
fsi
FSI1
FSI2
32.0 kHz
H
H
44.1 kHz
X
L
48.0 kHz
L
H
IFM1
Terminal
IFM2
Terminal
Word
Length
Data Sequence
Data Position
L
L
16 Bit
Backward packing
L
H
MSB first
H
L
20 Bit
Forward packing
H
H
LSB first
Backward packing
Output Format
OW20N
OW18N
16 Bit
H
H
18 Bit
Backward packing
H
L
20 Bit
L
H
Forward packing
L
L
Output Format
OW20N
OW18N
16 Bit
H
H
18 Bit
IIS Mode
H
L
20 Bit
Forward packing
L
H
L
L
SM-SX1H
– 40 –
34, 35
SLAVE
Input with pull-up resistor
Mode setting of BCKO, LRCO terminal. H: Output terminal is selected. (Slave mode)
L: Input terminal is selected. (Master mode)
L: Input terminal is selected. (Master mode)
36*,37* THRUN
Input with pull-up resistor
Through mode setting of DOUT
H: Normal mode, L: Through mode
38
OCKSL
Input with pull-up resistor
System clock on the output side (OCLK) selection. H: 384fs, L: 256fs
39
OCLK
Input
Output system clock input
40
LRCO
Input/Output
Word clock output/input on the output side (fso)
Output/input mode is set from the slave terminal.
Output/input mode is set from the slave terminal.
41, 42
BCKO
Input/Output
Bit clock output/input on the output side
Output/input mode is set from the slave terminal.
Output/input mode is set from the slave terminal.
43, 44
DOUT
Output
Data output
Pin No.
Port Name
Input/Output
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Function
IC801 VHiSM5844AF-1: Sampling Rate Converter (SM5844AF) (2/2)
Note 1: "fsi" means the word clock (LRCI) on the input side, and "fso" means the work clock (LRCO) on the output side.
Note 2: When H level is set, "open" is also applicable.
Note 3: When the terminal of plural terminal Nos. For the same terminal name is used, it does not matter whether either or both
Note 2: When H level is set, "open" is also applicable.
Note 3: When the terminal of plural terminal Nos. For the same terminal name is used, it does not matter whether either or both
terminals are connected.
Figure 40 BLOCK DIAGRAM OF IC
MCOM
MDT/FSI1
MCK/FSI2
MLEN/DEEM
ICLK
ICKSL
LRCI
RSTN
TST1N
TST2N
OW18N
OW20N
IISN
SLAVE
OCLK
OCKSL
THRUN
DMUTE
LRCO
BCKO
DOUT
STATE
IFM1
IFM2
BCKI
DI
MODE
De-emphasis
Attenuator Setting
Division on
the Input Side
Input Timing
Controller
Filter Characteristics
Selection
Output Practice
Timing Controller
Output Format
Controller
Clock Selection on the
Output Side
Dither
Division on the
Output Side
Mute
Generation
Direct Mute
Through Mode Switch
LRCI
BCKI
DI
Output Data
Interface
Output Operation
Interpolation
Filter Operation
Attenuator
Operation Section
De-emphasis
Operation
Input Data
Interface
16
17
18
19
20
6
7
5
30
31
28
29
22
21
24
23
25
26
34
35
39
38
36
37
14
15
40
41 42
43 44
27
2
1
4
3
11 10
8
9
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