Sharp SD-AT100 (serv.man6) Service Manual ▷ View online
– 103 –
SD-AT100H
77
TESM4
—
Test terminal.
78
VDD3
Input
3.3 V digital power supply.
79-82
BA0-4
Output
External RAM address output.
83
VSS5
—
5 V ground.
84-88
BA4-8
Output
External RAM address output.
89
VDD3
Input
3.3 V digital power supply.
90
/BOE
Output
External RAM/OE signal.
91
/BRAS
Output
External RAM/RAS signal.
92
/BCAS
Output
External RAM/CAS signal.
93
/BWL
Output
External RAM Lower/WE signal.
94
/BWU
Output
External RAM Upper/WE signal.
95
VDD5
Input
5 V power supply.
96-104
BD0-8
Input/Output
External RAM data input/output.
105
VSS3
—
3.3 V digital ground.
106-109
BD9-12
Input/Output
External RAM data input/output.
110
VSS5
—
5 V ground.
111-113
BD13-15
Input/Output
External RAM data input/output.
114*,115* N.C.
—
—
116
VDD3
Input
3.3 V digital power supply.
117
PLCK
Input/Output
PLL system clock input/output.
118,119
TESM5-6
—
Test terminal.
120*,121* TESM7-8
—
Test terminal.
122
VSS3
—
3.3 V digital ground.
123,124
CFC1,2
Output
VCO frequency control signal.
125
PPW
Output
Voltage output for phase comparator offset adjustment.
126
PESV
—
Signal input for phase comparator offset adjustment.
127
PVSS
—
3.3 V PLL system ground.
128
PESP
Output
Signal output for phase comparator offset adjustment.
129
PDOP1
Output
DVD/CD phase control signal. (positive polarity)
130
PDON1
Output
DVD/CD phase control signal. (negative polarity)
131
PDOP2
Output
DVD/CD phase control signal. (positive polarity)
132
PDON2
Output
DVD/CD phase control signal. (negative polarity)
133
LPFN
Input
Inversion input for data PLL low-pass filter.
134
LPFO
Output
Data PLL low-pass filter output.
135
PVREF
—
Reference power supply for data PLL system.
136
VCOREF
Input
VCO standard reference.
137
VCOF
Input
VCO auto adjustment filter output.
138
PVDD
Input
Power supply for 3.3 V PLL system.
139
SLCO1
Input/Output
Data slice 6-bit DAC output. (at differential input, RF On)
140*
TESM9
—
Test terminal.
141
TEST2
Input
Test mode terminal.
142
RFCD
Input
CD RF signal input. (at differential input, RF On)
143
RFDVD
Input
CD RF signal input. (at differential input, RF On)
144
AVDD
Input
Power supply for 3.3 V analog system.
145*
RFCT
Input
RFRP center voltage input. (zero cross import)
146
RFZI
Input
RFRP zero cross signal input.
147
TEZI
Input
Tracking error signal input. (zero cross import)
148
AWIN
Input
Signal input for active wide PLL control.
149
AVSS
Input
Power supply for 3.3 V analog system.
150
FEI
Input
Focus error signal input.
151
TEI
Input
Tracking error signal input.
152
RFSB
Input
Add input for RF level or sub beam signal.
IC3701 VHiTC94A03F-1: Servo ECC (TC94A03F) (2/3)
Pin No.
Function
Terminal Name Input/Output
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
SD-AT100H
– 104 –
Figure 104 BLOCK DIAGRAM OF IC
153
RFRP
Input
RFRP signal input.
154
AVSS
Input
Power supply for 3.3 V analog system.
155
TESM10
—
Test terminal.
156
EXTAD
Input
General-purpose external ADC input.
157
VREF
Input
Reference power supply for analog system: 1.65 V.
158
FOO
Output
Focus EQ output.
159
TRO
Output
Tracking EQ output.
160
AVDD
Input
Power supply for 3.3 V analog system.
161
AWCTL
Output
Active wide PLL control output.
162
FMO
Output
Feed EQ output.
163
DMO
Output
Disc EQ output.
164
TEBC
Output
Tracking balance control signal.
165*
FEBC
Output
Focus balance control signal.
166
DPDC
Output
Pit depth adjustment signal of DPD error signal.
167
EQBC
Output
Boost adjustment signal for RF wide area.
168
ANMON
Output
General-purpose PWM output.
169
/DFCT
Output
Black dot detection signal.
170
VRCK
Output
RF EQ characteristics control clock.
171
VSS3
—
3.3 V digital ground.
172
SCD
Output
Head amp serial data.
173
SCL
Output
Head amp serial latch pulse.
174
SCB
Output
Head amp serial data clock.
175*
FGIN
Input
Disc FG signal input. (with self-bias circuit).
176
ASLCP
Output
Data slice positive output.
IC3701 VHiTC94A03F-1: Servo ECC (TC94A03F) (3/3)
Pin No.
Function
Terminal Name Input/Output
The terminal whose name starts with “/” is activated in “L”.
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Servo signal
from RF amp
from RF amp
RF signal
from RF amp
ADC
DEQ
Servo
Control
DAC I/F
DAC
to Driver, RF amp
Digital
in
Analog
out
1bit DAC
for
CD-DA
Clock
PLL
Micom BUS
Micom
I/F
to Micom
to DECORDER
Output
I/F
ECC
DRAM
I/F
to DRAM
Syndrome
operation
SYNC Dat.
Demodulation
Slice
level
Gen.
Data
Slicer
PLL
to RF amp
Digital Servo
– 105 –
SD-AT100H
1
GND
—
GND terminal.
2
P2TP
Input
TE+ input. (CD)
3
P2TN
Input
TE– input. (CD)
4
LDO2
Output
Drive output 2.
5
MDI2
Input
Monitor input 2.
6
VrD
Output
Digital VREF.
7
Vrfil
—
Filter capacity for reference.
8
Vdd
Input
Power terminal.
9
DPAC
—
DPD AC combination capacity 1.
10
DPBD
—
DPD AC combination capacity 2.
11
DPD1
—
DPD integral capacity 1.
12
DPD2
—
DPD integral capacity 2.
13
SCB
Input
Control line. (Bit clock)
14
SCL
Input
Control line. (Latch signal)
15
SCD
Input
Control line. (Sirial Data)
16
VRCK
Input
Reference clock input.
17
VCKF
—
Capacity for VRCK time constant adjustment.
18
VccP
Input
Power terminal.
19
LVL
Output
Servo addition output.
20
TEO
Output
TE output.
21
FEO
Output
FE output.
22
DFTN
Input
DPD difect.
23
VccS
Input
Power terminal. (servo)
24*
N.C.
—
—
25
RPZ
Output
RF ripple output 2.
26
RPO
Output
RF ripple output 1.
27
RPB
—
RF ripple bottom.
28
RPP
—
RF ripple peak.
29
RFOn
Output
Equivalent RF output. (Differential output)
30
RFOp
Output
Equivalent RF output. (Differential output)
31
VccR
Input
Power terminal. (RF)
32
RFS
Input
RF slice level adjustment.
33
TEB
Input
TE balance.
34
FEB
Input
FE balance.
35
DPDB
Input
Pit depth adjustment.
36
Vcc2
Input
Power terminal.
37*
N.C.
—
—
38*
N.C.
—
—
39
GND2
—
GND terminal.
40
TCC1
Input
Time constant adjustment.
41
RFDC
—
DC feedback capacity.
42
VrA
Output
Analog VREF.
43
EQB
Input
Boost adjustment.
44
EQF
Input
Frequency adjustment.
45
MDI1
Input
Monitor input 1.
46
LDO1
Output
Drive output 1.
47
P1TN
Input
TE– input. (DVD)
49
P1FN
Input
FE– input. (DVD)
50
P1FP
Input
FE+ input. (DVD)
51
LDP1
Input
APC polarity 1.
52
P1DI
Input
D input. (DVD)
IC3301 VHiTA1323F+-1: RF Signal Processor (TA1323F) (1/2)
Terminal Name
Pin No.
Input/Output
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
SD-AT100H
– 106 –
53
P1CI
Input
C input. (DVD)
54
P1BI
Input
B input. (DVD)
55
P1AI
Input
A input. (DVD)
56
GNDR
—
GND terminal. (RF)
57
LDP2
Input
APC polarity 2.
58
P2AI
Input
A input. (CD)
59
P2BI
Input
B input. (CD)
60
P2CI
Input
C input. (CD)
61
P2DI
Input
D input. (CD)
62
GNDS
—
GND terminal. (Servo)
63
P2FP
Input
FE+ input. (CD)
64
P2Fn
Input
FE– input. (CD)
IC3301 VHiTA1323F+-1: RF Signal Processor (TA1323F) (2/2)
Terminal Name
Pin No.
Input/Output
Function
Figure 106 BLOCK DIAGRAM OF IC
P1TP
P1TN
LDO1
MDI1
EQF
EQB
VrA
RFDC
TCC1
GND2
NC
NC
Vcc2
DPDB
FEB
TEB
RFS
VccR
RFOp
RFOn
RPP
RPB
RPO
RPZ
NC
VccS
DFTN
FEO
TEO
LVL
VccP
VCKF
P1FN
P1FP
LDP1
P1DI
P1CI
P1BI
P1AI
GNDR
LDP2
P2AI
P2BI
P2CI
P2DI
GNDS
P2FP
P2FN
GND
P2TP
P2TN
LDO2
MDI2
V
rD
V
rfil
V
dd
DPAC
DPBD
DPD1
DPD2
SCB
SCL
SCD
V
RCK
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Time
constant
adjustment
RF Ripple
creation
Output
Amp
T-gain
Adjust
Adjust
sel-PD
sel-PD
sel-PD
Level
detect
F-gain
Adjust
Adjust
mode-IC
R-gain
Adjust
3Beam-TE
creation
DPD-TE
creation
FE creation
EQ
APC1
APC2
Vref
BUS
sel-RF
sel-FE
sel-TE
sel-DPD
sel-LVL
mode-TE
F-gain
Adjust
Adjust
DPDB
TEB
FEB
TEB
TCC1
VrA
tcc1 (BUS)
TE-gain
Adjust
FE-gain
Adjust
DC
FB
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