Sharp CD-MD3000 (serv.man25) Service Manual ▷ View online
CD-MD3000H/CD-MD3000W
– 102 –
IC1201 VHiLR37814/-1: Endec/Atrac (LR37814)
Figure 102-2 BLOCK DIAGRAM OF IC
Figure 102-1 BLOCK DIAGRAM OF IC
IC1101 VHiiR3R58M/-1:RF Signal Processor (IR3R58M)
MODE
SW
BPF
BIAS
ADIP AGC
DIFF
RESISTOR & SW
EFM AGC
RF1
RF2
RF3
RF4
REFI
REFO
AOUT
ASW
AIN
BIN
BSW
BOUT
2-1
ADAGI
ADAGC
ADIPNF
ADIPO
GND2
WBO
VCC2
OPICPW
DISC
SGAIN
DTEMP
1234
1+2
PIN
3+4
PITG
NIN
GND1
BIAS
VCC1
EFMAGC
DCNF
EFMO
EOUT
ESW
EIN
FIN
FSW
FOUT
EOUT
BOUT
AOUT
TCGO
TCGI
RFADD
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
13
14
15
16
17
18
19
20
21
22
23
24
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
TOTMON
TEMCN
SBCK
SBO
SBSY
SFSY
FCK
SENSE
COUT
MCCK
DINIX
VDD2
VDD2
DGND
RSTX
SYD0
SYD1
SYD2
SYD3
SYD4
SYD5
SYD6
SYD7
SYD1
SYD2
SYD3
SYD4
SYD5
SYD6
SYD7
SYWRX
SYRDX
SYRS
EFMO
PLCK
ACRCEF
RAA11
RAD0
RAD1
RAWEX
RARASX
RAA9
RAD3
RAD2
RACASX
DGND
RACEX
RAA8
RAA7
RAA6
RAA5
RAA4
VDD2
RAA10
RAA0
RAA1
RAA2
RAA3
PLCK
ACRCEF
RAA11
RAD0
RAD1
RAWEX
RARASX
RAA9
RAD3
RAD2
RACASX
DGND
RACEX
RAA8
RAA7
RAA6
RAA5
RAA4
VDD2
RAA10
RAA0
RAA1
RAA2
RAA3
EFMMON
AVCC1
EFM1
AGND1
AVCC2
VREF
WBI
TCG
AIN
BIN
EIN
FIN
VBAT
VDD1
DGND
TEST2
X176KO
FODRF
FODRR
TRDRF
TRDRR
SLDRF
SLDRR
SPDRF
SPDRR
FEMON
DADATA
ADDATA
DFCK
BCLK
LRCK
DGND
PLLBVC
DOUT
DIN
XO
XI
DGND
VDD1
VPO
VXI
CDBCLK
CDLRCK
CDDATA
DIN2
DILOCK
TEST1
TEST0
TCRS
X700KO
LR37814
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
– 103 –
CD-MD3000H/CD-MD3000W
1*
EFMMON
Output
EFM monitor output
2
AVCC1
–
Analog power supply (for EFM system 8AD, 8DA)
3
EFMI
Input
EFM signal input from RF amplifier
4
AGND1
–
Analog GND
5
AVCC2
–
Analog power supply (for servo system, ADIP system 1bit AD)
6
VREF
Input
Reference voltage input for RF amplifier
7
WBI
Input
ADIP wobble signal
8
TCG
Input
Track cross signal
9
AIN
Input
Focus error signal A
10
BIN
Input
Focus error signal B
11
EIN
Input
Tracking error signal E
12
FIN
Input
Tracking error signal F
13
VBAT
Input
Power voltage detection signal for constant voltage servo
14
VDD1
–
Internal digital power supply
15
DGND
–
Digital GND
16
TEST2
Input
Input for test. Connected to GND if used normally
17*
X176KO
Output
Clock output. f=176.4KHz (4fs)
18
FODRF
Output
Focus servo forward output. PWM.
19
FODRR
Output
Focus servo reverse output. PWM.
20
TRDRF
Output
Tracking servo forward output. PWM.
21
TRDRR
Output
Tracking servo reverse output. PWM.
22
SLDRF
Output
Slide servo forward output. PWM.
23
SLDRR
Output
Slide servo reverse output. PWM.
24
SPDRF
Output
Spindle servo forward output. PWM.
25
SPDRR
Output
Spindle servo reverse output.
26
RAA3
Output
Address output to external D-RAM. ADR3
27
RAA2
Output
Address output to external D-RAM. ADR2
28
RAA1
Output
Address output to external D-RAM. ADR1
29
RAA0
Output
Address output to external D-RAM. ADR0 (LSB)
30*
RAA10
Output
Address output to external D-RAM. ADR10 (MSB)
31
VDD2
–
Power supply for interface
32
RAA4
Output
Address output to external D-RAM. ADR4
33
RAA5
Output
Address output to external D-RAM. ADR5
34
RAA6
Output
Address output to external D-RAM. ADR6
35
RAA7
Output
Address output to external D-RAM. ADR7
36
RAA8
Output
Address output to external D-RAM. ADR8
37
RAOEX
Output
Data output enable signal output to external D-RAM
38
DGND
–
Digital GND
39
RACASX
Output
Column address strobe signal output to external D-RAM
40
RAD2
Input/Output
Data input and output with external D-RAM. D2
41
RAD3
Input/Output
Data input and output with external D-RAM. D3 (MSB)
42
RAA9
Output
Address output to external D-RAM. ADR9
43
RARASX
Output
Low address strobe signal output to external D-RAM
44
RAWEX
Output
Data write enable signal output to external D-RAM
45
RAD1
Input/Output
Data input and output with external D-RAM. D1
46
RAD0
Input/Output
Data input and output with external D-RAM. D0 (LSB)
47*
RAA11
Output
Address output to external D-RAM. ADR11 (MSB 64 Mbit)
48*
ACRCER
Output
CRC error flag monitor output of ADIP
49*
PLCK
Output
Playback mode: EFM PLL clock output
50
EFM0
Output
Recording mode: EFM signal output. Playback mode: C1F (C1 error flag) monitor output.
51*
X700KO
Output
Clock output. f=705.6KHz
IC1201 VHiLR37814/-1: Endec/Atrac (LR37814) (1/2)
Pin No.
Function
Terminal Name Input/Output
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
CD-MD3000H/CD-MD3000W
– 104 –
52*
TCRS
Output
Track cross signal
53
TEST0
Input
Input for test. Connected to GND if used normally.
54
TEST1
Input
Input for test. Connected to GND if used normally.
55
DILOCK
Output
DIN lock detection
56
DIN2
Input/Output
Digital input signal. Expansion port 0.
57
CDDATA
Input/Output
Data input for dubbing. Expansion output port 1.
58
CDLRCK
Input/Output
LR clock input for dubbing. Expansion output port 2.
59
CDBCLK
Input/Output
Bit clock input for dubbing. Expansion output port 3.
60
VXI
Input
PLL clock input for variable pitch
61*
VPO
Output
PLL phase error output for variable pitch
62
VDD1
–
Internal digital power supply
63
DGND
–
Digital GND
64
XI
Input
Transmit circuit input. 33.8688MHz
65
XO
Output
Transmit circuit input. 33.8688MHz
66
DIN
Input
Digital input signal
67
DOUT
Output
Digital output signal
68
PLLBVG
Output
For Internal PLL. Terminal for external capacitor
69
DGND
–
Digital GND
70
LRCK
Output
L-ch, R-ch selection output of music data
71
BCLK
Output
Shift lock of music data
72
DFCK
Output
Clock for AD/DA converter digital filter. 256Fs.
73
ADDATA
Input
Sound data input.
74
DADATA
Output
Sound data output.
75*
FEMON
Output
Focus error signal monitor output. Series resistance 10 - 100K
Ω
built-in
76*
TOTMON
Output
Total signal monitor output. Series resistance 10 - 100K
Ω
built-in
77*
TEMON
Output
Tracking error signal monitor output. Series resistance 10 - 100K
Ω
built-in
78
SBCK
Input/Output
DIN subcode read clock. Expansion port 4.
79
SBO
Output
DIN subcode serial data. Expansion port 5.
80
SBSY
Output
DIN subcode block synchronous signal. Expansion port 6.
81
SFSY
Output
DIN subcode frame synchronous signal. Expansion port 7.
82
FOK
Output
Focus OK detection signal. “0”: focus OK
83
SENSE
Output
Servo condition detection signal
84
COUT
Output
Track cross signal output
85
MCCK
Output
Clock output for microcomputer
86
DINTX
Output
Interrupt request output terminal to system computer interface
87
VDD2
–
Power supply for interface
88
DGND
–
Digital GND
89
RSTX
Input
Chip reset input. Reset by L. (Note)
90
SYD0
Input/Output
Data bus terminal of system computer interface (LSB)
91~96
SYD1~SYD6
Input/Output
Data bus terminal of system computer interface
97
SYD7
Input/Output
Data bus terminal of system computer interface (MSB)
98
SYWRX
Input
Resister write pulse input of system computer interface
99
SYRDX
Input
Resister read pulse input of system computer interface
100
SYRS
Input
Resister selection input of system computer interface
IC1201 VHiLR37814/-1: Endec/Atrac (LR37814) (2/2)
Pin No.
Function
Terminal Name Input/Output
Note: Set RSTX to L when turning on the power or after turning on the power.
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
– 105 –
CD-MD3000H/CD-MD3000W
IC1202 RH-iX2474AFZZ: 4Mbit D-RAM (IX2474AF)
Pin No.
Function
Terminal Name
1, 2
I/O1, I/O2
Data input/Data output
3
WE
Write enable
4
RAS
Row address storobe
5
A9
Address input
6-9
A0-A3
Address input
10
Vcc
Power (3.3V)
11-15
A4-A8
Address input
16
OE
Output enable
17
CAS
Column address storobe
18, 19
I/O3, I/O4
Data input/Data output
20
GND
Ground
Figure 105-1 BLOCK DIAGRAM OF IC
IC1301 VHiFTD2005/-1: Head Driver (FTD2005)
IC1302 VHiCPH5608/-1: Head Driver (CPH5608)
D2
S2
S2
G2
D1
S1
S1
G1
5
6
7
8
4
3
2
1
G1
S
G2
D1
D2
1
2
3
4
5
Figure 105-2 BLOCK DIAGRAM OF IC
Figure 105-3 BLOCK DIAGRAM OF IC
IC1402 VHi58X2402T-1: EEPROM (58X2402T)
Pin No.
Function
Terminal Name
1-3
A0~A2
Device address
4
VSS
Ground
5
SDA
Serial data input/output
6
SCL
Serial clock input
7
WP
Write protect
8
VCC
Power supply
Figure 105-4 BLOCK DIAGRAM OF IC
1
2
3
4
8
7
6
5
A0
A1
A2
VSS
VCC
WP
SCL
SDA
4
RAS
5
17
15
CAS
A0
A9
WE
DQ0~DQ3
20
V
SS
V
BB
17
CAS
Clock Generator
CBR Refresh
Counter
Row Address
Buffer
Memory
Cell
I/O
Selection
Write Clock
Generator
Data Input
Buffer
Data Output
Buffer
Row Address
Buffer
On ChipVBB
Generator
Row Decoder
Column Decoder
Sense Amp.
Word Driver
SELF Refresh
Timer
MN42V4400 Only
3
OE
16
2
18
19
1
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