Sharp CD-C440H (serv.man2) Service Manual ▷ View online
– 45 –
CD-C440H/CP-C440H
• Checking the spin system.
Yes
No
Play operation is performed without disc.
The turntable rotates a little.
The turntable fails to rotate or rotates at high speed.
Yes
The spin driver circuit is normal.
Check the periphery of IC1 pins 23 to 27, pin 39, and pin 40, IC2
pin 12 and pin 13, IC5 to CNP3.
pin 12 and pin 13, IC5 to CNP3.
Yes
• Checking the VCO-PLL system
Figure 45
Play operation is performed when disc exits.
Yes
Although HF waveform is normal, TOC data cannot be read.
Yes
Check PDO waveform (Fig. 45).
Abnormal
Check the IC1 pins 43 and 44, IC2 pins 3, 5, 7, 10, and 11.
Stop --> Play
As VCO freque-
ncy is locked at
4.32 M Hz, voltage
of PDO rises and
stabili- zes.
ncy is locked at
4.32 M Hz, voltage
of PDO rises and
stabili- zes.
2
3
0.5s
1.00 V
IC2 3 PDO
1.00 V
IC2 3 PDO
0.5s
1.00 V
IC2 16 FD
1.00 V
IC2 16 FD
• Although HF waveform is normal and the time
indication is normal, no sound is emitted.
Check IC 2 pin 48 (EFLG).
Check IC2 pins 37, 40.
Check IC 501 and POWER AMP IC 901.
Abnomal
Yes
Usually, the number of pulses of flawless disc is 100 pulses/sec
or less.
or less.
No
CD-C440H/CP-C440H
– 46 –
1
DEFI
Input
Input terminal of defect detection signal (DEF). (Connected to OV when not used.)
2
TAI
Input
For PLL
Input terminal for test. Pull-down resistor is integrated. Surely connected to 0V.
3
PDO
Output
Output terminal of phase comparison for external VCO control.
4
VVSS
—
Ground terminal for integrated VCO. Surely connected to 0V.
5
ISET
Input
Resistance connection terminal for current adjustment of PDO output.
6
VVDD
—
Power terminal for integrated VCO.
7
FR
Input
VCO frequency range adjustment.
8
VSS
—
Ground terminal of digital system. Surely connected to 0V.
9
EFMO
Output
For slice level control
EFM signal output terminal.
10
EFMIN
Input
EFM signal input terminal.
11
TEST2
Input
Input terminal for test. Pull-down resistor is integrated. Surely connected to 0V.
12
CLV+
Outout
Output for disk motor control. 3 values can be output with the commands.
13
CLV-
Output
Output for disk motor control. 3 values can be output with the commands.
14
V/P
Output
Monitor output terminal for automatic switch of rough servo/phase control.
"H" for rough servo, and "L" for phase servo.
"H" for rough servo, and "L" for phase servo.
15
HFL
Intput
Input terminal of track detection signal. Schmit input.
16
TES
Input
Input terminal of tracking error signal. Schmit input.
17
TOFF
Output
Tracking OFF output terminal.
18
TGL
Output
Output terminal for switch of tracking gain "L" increases the gain.
19
JP+
Output
Output for track jump control. 3 values can be output with the commands.
20
JP-
Output
Output for track jump control. 3 values can be output with the commands.
21*
PCK
Output
Clock monitor terminal for EFM data replay. 4,3218MHz as the phase clock.
22*
FSEQ
Output
Output terminal synchronous signal detection. "H" is output when synchronous signal detected
by EFM signal matches synchronous signal internally generated.
by EFM signal matches synchronous signal internally generated.
23
VDD
—
Power terminal of digital system.
24
CONT1
Input/Output
General purpose input/output terminal 1
25
CONT2
Input/Output
General purpose input/output terminal 2
26
CONT3
Input/Output
General purpose input/output terminal 3
27
CONT4
Input/Output
General purpose input/output terminal 4
28*
CONT5
Input/Output
General purpose input/output terminal 5
29*
EMPH
Output
Difference monitor terminal At "H", deemphasis disk is being replayed.
30*
C2F
Output
C2 flag output terminal.
31*
DOUT
Output
Output terminal of digital OUTPUT. (EIAJ format)
32*
TEST3
Input
Input terminal for test. Pull-down resistor is integrated. Surely connected to 0V.
33
TEST4
Input
Input terminal for test. Pull-down resistor is integrated. Surely connected to 0V.
34*
N.C.
—
Terminal not used. Open during operation.
35*
MUTEL
Output
L channel 1 bit DAC
Mute output terminal for L channel.
36
LVDD
—
Power terminal for L channel.
37
LCHO
Output
L channel output terminal.
38
LVSS
—
Ground terminal for L channel Surely connected to 0V.
39
RVSS
—
R channel 1 bit DAC
Ground terminal for R channel Surely connected to 0V.
40
RCH0
Output
R channel output terminal.
41
RVDD
—
Power terminal for R channel.
42*
MUTER
Output
Mute output terminal for R channel.
43
XVDD
—
Power terminal for quartz oscillation.
44
XOUT
Output
Ground terminal of 16.9344 MHz quartz oscillator.
45
XIN
Input
Ground terminal of 16.9344 MHz quartz oscillator.
46
XVSS
—
Ground terminal for quartz oscillation. Surely connected to 0V.
47*
SBSY
Output
Output terminal of synchronous signal of subcode block.
48*
EFLG
Output
Correction monitor terminal of C1, C2, single and double.
FUNCTION TABLE OF IC
Pin No.
Function
Terminal Name
Input/Output
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Controlled with serial data command
from micro computer.
When not used, set it as the input terminal and
open it by connecting to 0V, or set it as the output
terminal and open it.
from micro computer.
When not used, set it as the input terminal and
open it by connecting to 0V, or set it as the output
terminal and open it.
IC2 VHiLC78623E-1:Servo/Signal Control(LC78623E) (1/2)
– 47 –
CD-C440H/CP-C440H
Function
Terminal Name Input/Output
49*
PW
Output
Output terminal of subcodes P, A, R, S, T, U and W.
50*
SFSY
Output
Output terminal of synchronous signal of subcode frame. It drops when subcode stands by.
51
SBCK
Input
Clock input terminal to read subcode. Schmit input (Connected to 0V when not used.)
52*
FSX
Output
Output terminal of synchronous signal of 7.35kHz divided from quartz oscillation.
53
WRQ
Output
Output terminal to stand by output of subcode Q.
54
RWC
Input
Input terminal of read/write. Schmit input.
55
SQOUT
Output
Output terminal of subcode Q.
56
COIN
Input
Command input terminal from microcomputer.
57
CQCK
Input
Clock input terminal to fetch command input, or pick up subcode from SQOUT. Schmit input
58
RES
Input
Reset input terminal of LC78622. When turning on power, set it at "L".
59*
TST11
Output
Output terminal for test. Used in the open state ("L" output as ordinary).
60*
16M
Output
Output terminal of 16.9344Hz.
61
4.2M
Output
Output terminal of 4.2336MHz.
62
TEST5
Input
Input terminal for test Pull-down resistor is integrated. Surely connected to 0V.
63
CS
Input
Chip selection input terminal. Pull-down resistor is integrated.
Connected to 0when not controlled.
Connected to 0when not controlled.
64
TEST1
Input
Input terminal for test Pull-down resistor is integrated. Surely connected to 0V.
Pin No.
Note: The same potential must be supplied to the power terminals (VDD, VVDD, LVDD, RVDD, XVDD).
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
DEFI
EFMIN
FSEQ
V/P
PW
SBCK
SBSY
SFSY
CS
WRQ
SQOUT
COIN
RWC
CQCK
HFL
TES
TOFF
JP-
JP+
RES
TGL
CONT1
CONT2
CONT3
CONT4
CONT5
EMPH
EFLG
16M
4.2M
XVss
FSX
XIN
XOUT
XV
DD
RVss
RV
DD
MUTER
RCHO
LCHO
MUTEL
LVss
LV
DD
(NC)
DOUT
C2F
EFMO
VV
DD
VVss
PDO
I SET
FR
PCK
TAI
TSTI1
TEST1
TEST2
TEST3
TEST4
TEST5
V
DD
Vss
CLV+
CLV-
Slice level
control
VCO colck oscillation
clock control
2 K x 8 b i t
R A M
RAM address
generator
Interpolation mute
Bilingual
Digital OUT
Digital
attenuator
X4 oversampling
digital filter
1 b i t D A C
L . P . F
XTAL system timing
generator
General-use port
Servo commander
É C O M
Interface
Subcode division
QCRC
C L V
Digital servo
Sync detection
EFM demodulation
Flag processing of C1/C2
error detection and correction
Figure 47 BLOCK DIAGRAM OF IC
IC2 VHiLC78623E-1:Servo/Signal Control(LC78623E) (2/2)
CD-C440H/CP-C440H
– 48 –
IC1 VHiLA9240M/-1:Servo Amp. (LA9240M) (1/2)
1
FIN2
Connection pin for photodiode of pickup.
RF signal is generated through addition with FIN pin, and FE signal is generated through subtraction.
RF signal is generated through addition with FIN pin, and FE signal is generated through subtraction.
2
FIN1
Connection pin for photodiode of pickup.
3
E
Connection pin for photodiode of pickup. TE signal is generated through subtraction with F pin.
4
F
Connection pin for photodiode of pickup.
5
TB
Pin for input of DC component of TE signal.
6
TE-
Pin to connect gain setting resistor of TE signal to TE signal.
7
TE
TE signal output pin.
8
TESI
TES (Track error sense) comparator input pin. TE signal is band-passed and input.
9
SCI
Input pin for shock detection.
10
TH
Pin to set time constant of tracking gain.
11*
TA
TA amplifier output pin.
12
TD-
Pin to compose tracking phase compensation constant between TD and VR pins.
13
TD
Pin to set tracking phase compensation.
14
JP
Pin to set amplitude of tracking jump signal (kick pulse).
15
TO
Tracking control signal output pin.
16
FD
Focusing control signal output pin.
17
FD-
Pin to compose focusing phase compensation constant between FD and FA pins.
18
FA
Pin to compose focusing phase compensation constant between FD-/FA-pins.
19
FA-
Pin to compose focusing phase compensation constant between FA and FE pins.
20
FE
Output pin of FE signal.
21
FE-
Pin to connect gain setting resistor of FE signal across TE pin.
22
AGND
GND for analog signal.
23
SP
Single end output for CV+ and CV- pin input.
24
SPI
Spindle amplifier input.
25
SPG
Pin to connect gain setting resistor in the 12cm mode of spindle.
26
SP-
Pin to connect spindle phase compensation constant together with SPD pin.
27
SPD
Spindle control signal output pin.
28
SLEQ
Pin to connect thread phase compensation constant.
29
SLD
Thread control signal output pin.
30
SL-
Input pin of thread feed signal from micro computer.
31
SL+
Input pin of thread feed signal from micro computer.
32
JP-
Input pin of tracking jump signal from DSP.
33
JP+
Input pin of tracking jump signal from DSP.
34
TGL
Input pin of tracking gain control signal from DSP. TGL = Gain low at "H"
35
TOFF
Input pin of tracking off control signal from DSP. TOFF = Off at "H"
36
TES
Output pin of TES signal to DSP.
37
HFL
(HIGH FREQUENCY LEVEL) is used to judge whether main beam is positioned on the bit or on the mirror.
38
SLOF
Thread servo off control input pin.
39
CV-
Pin to input CLV error signal from DSP.
40
CV+
Pin to input CLV error signal from DSP.
41
RFSM
RF output pin.
42
RFS-
Pin to set gain of RF and set 3T compensation constant together with RFSM pin.
43
SLC
(SLICE LEVEL CONTROL) is the output pin to control of the level of the data slice with RF waveform DSP.
44
SLI
Input pin to control the level of data slice with DSP.
45
DGND
GND pin in the digital system.
46
FSC
Output pin for focus search smoothening capacitor.
47
TBC
(Tracking Balance Control) Pin to set EF balance variable range.
48*
NC
No connect.
49
DEF
Defect detection output pin of disk.
50
CLK
Reference clock input pin. 4.23MHz of DSP is input.
Pin No.
Port Name
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
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