Panasonic KX-UT670RU Service Manual ▷ View online
81
KX-UT670RU
14 Appendix Information of Schematic Diagram
Note:
1. DC voltage measurements are taken with an oscilloscope or a tester with a ground.
1. The schematic diagrams and circuit board may be modified at any time with the development of new technology.
1. The schematic diagrams and circuit board may be modified at any time with the development of new technology.
82
KX-UT670RU
15 Exploded View and Replacement Parts List
15.1. IC Data
15.1.1. IC1
Although these blocks below are divided into 5 since they were taken from 12 Schematic Diagram, in actual fact, IC1 is composed
of these all 5 blocks.
of these all 5 blocks.
Pin No.
Terminal name
Function
I/Osetting
Contents Control
remark
A1
VSS_1
VSS
GND
Ground
A2
DDR_VDDO_1
DDR_VDDO
P
DDR2 I/O supply -1.8V
A3
VSS_2
VSS
GND
Ground
A4
DDR_A9
DDR_A9
O
DDR2 address bus
A5
VSS_3
VSS
GND
Ground
A6
DDR_A3
DDR_A3
O
DDR2 address bus
A7
DDR_A1
DDR_A1
O
DDR2 address bus
A9
DDR_CKE
DDR_CKE
O
DDR2 clock enable
A10
DDR_DQ8
DDR_DQ8
IO
DDR2 data bus
A12
DDR_DQ9
DDR_DQ9
IO
DDR2 data bus
A13
DDR_DQ0
DDR_DQ0
IO
DDR2 data bus
A14
DDR_DQ7
DDR_DQ7
IO
DDR2 data bus
A16
DDR_DQ6
DDR_DQ6
IO
DDR2 data bus
A17
BBL_XTALO
XTAL
IO
32.768 kHz reference XTAL input
A18
SREG1P8_NDRV
SREG1P8_NDRV
O
1.8V switching power supply N-ch FET gate drive
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KX-UT670RU
A19
SREG1P2_NDRV
SREG1P2_NDRV
O
1.2V switching power supply N-ch FET gate drive
A20
VREG2P5_VDD_3P3
VREG2P5_VDD
P
2.5V regulator input(Connect to 3.3V)
A22
USB0_DP
USB0_DP
IO
USB 2.0 port0 data pair, host only
A23
USB1_DP
USB1_DP
NC
Not in use
A24
USB_AVDD_3P3
USB_AVDD
P
USB analog supply-3.3V
A25
VSS_4
VSS
GND
Ground
B1
DDR_VDDO_2
DDR_VDDO
P
DDR2 I/O supply -1.8V
B2
VSS_5
VSS
GND
Ground
B3
DDR_A14
DDR_A14
NC
Not in use
B4
DDR_A12
DDR_A12
O
DDR2 address bus
B5
DDR_A7
DDR_A7
O
DDR2 address bus
B6
DDR_A5
DDR_A5
O
DDR2 address bus
B7
DDR_VDDO_3
DDR_VDDO
P
DDR2 I/O supply -1.8V
B8
DDR_BA1
DDR_BA1
O
DDR2 bank address
B9
DDR_WE_B
DDR_WE_B
O
DDR2 write enable
B10
DDR_VDDO_4
DDR_VDDO
P
DDR2 I/O supply -1.8V
B11
DDR_CK1_P
DDR_CK
O
DDR2 differential clock 1
B12
DDR_DQ14
DDR_DQ14
IO
DDR2 data bus
B13
DDR_VDDO_5
DDR_VDDO
P
DDR2 I/O supply -1.8V
B14
DDR_CK0_P
CLK
O
DDR2 differential clock 0
B15
DDR_DQS0_N
DDR_DQS0_N
IO
DDR2 differential data strobe
B16
DDR_VDDO_6
DDR_VDDO
P
DDR2 I/O supply -1.8V
B17
BBL_XTALI
XTAL
IO
32.768 kHz reference XTAL input
B18
SREG1P8_PDRV
SREG1P8_PDRV
IO
1.8V switching power supply P-ch FET gate drive
B19
SREG1P2_PDRV
SREG1P2_PDRV
IO
1.2V switching power supply P-ch FET gate drive
B20
VDDO_1
VDDO
P
Digital I/O supply-3.3V
B21
USB_RREF
RREF
IO
Connect a 4.02K
Ω resitor and a100pF capacitor in parallel
between this pin and ground
B22
USB0_DM
USB0_DM
IO
USB 2.0 port0 data pair, host only
B23
USB1_DM
USB1_DM
NC
Not in use
B24
CLD3
CLD3
IO
PIF data bit 3
B25
VSS_6
VSS
GND
Ground
C1
DDR_VREF
DDR_VREF
I
DDR2 SSTL_18 reference voltage
C2
DDR_ZQ
DDR_ZQ
I
Connect to ground through a 240
Ω, 1% resistor
C3
VSS_7
VSS
GND
Ground
C4
DDR_A11
DDR_A11
O
DDR2 address bus
C5
DDR_A8
DDR_A8
O
DDR2 address bus
C6
DDR_A4
DDR_A4
O
DDR2 address bus
C7
DDR_A0
DDR_A0
O
DDR2 address bus
C8
DDR_A10
DDR_A10
O
DDR2 address bus
C9
DDR_BA0
DDR_BA0
O
DDR2 bank address
C10
DDR_DM1
DDR_DM1
O
DDR2 data mask for upper byte
C11
DDR_CK1_N
DDR_CK
O
DDR2 differential clock 1
C12
DDR_DQS1_N
DDR_DQS1
IO
DDR2 differential data strobe
C13
DDR_DM0
DDR_DM0
O
DDR2 data mask for lower byte
C14
DDR_CK0_N
DDR_CK
O
DDR2 differential clock 0
C15
DDR_DQS0_P
DDR_DQS0
IO
DDR2 differential data strobe
C16
DDR_DQ2
DDR_DQ2
IO
DDR2 data bus
C17
BBL_PWRGOOD
BBL_PWRGOOD
I
BBL power good
C18
SREG1P8_SENSE
SREG1P8_SENSE
IO
1.8V switching power supply sense
C19
SREG1P2_SENSE
SREG1P2_SENSE
IO
1.2V switching power supply sense
C20
NC1
NC
NC
Not in use
C21
NC2
NC
NC
Not in use
C22
USB_AVSS_1
USB_AVSS
GND
USB Analog Ground
C23
CLD1
CLD1
IO
PIF data bit 1
C24
CLD10
CLD10
IO
PIF data bit 10
C25
CLD14
CLD14
IO
PIF data bit 14
D1
PLL_VSS_1
PLL_VSS
GND
PLL Ground
D2
PLL_VSS_2
PLL_VSS
GND
PLL Ground
D3
NC7
NC
NC
Not in use
D4
DDR_A13
DDR_A13
O
DDR2 address bus
D5
VSS_8
VSS
GND
Ground
D6
DDR_A6
DDR_A6
O
DDR2 address bus
D7
DDR_CAS_B
DDR_CAS
O
DDR2 column address strobe
D8
DDR_BA2
DDR_BA2
O
DDR2 bank address
D9
DDR_RAS_B
DDR_RAS
O
DDR2 row address strobe
D10
DDR_DQ13
DDR_DQ13
IO
DDR2 data bus
Pin No.
Terminal name
Function
I/Osetting
Contents Control
remark
84
KX-UT670RU
D11
DDR_DQ15
DDR_DQ15
IO
DDR2 data bus
D12
DDR_DQS1_P
DDR_DQS1
IO
DDR2 differential data strobe
D13
DDR_DQ12
DDR_DQ12
IO
DDR2 data bus
D14
DDR_DQ1
DDR_DQ1
IO
DDR2 data bus
D15
DDR_DQ3
DDR_DQ3
IO
DDR2 data bus
D16
DDR_DQ5
DDR_DQ5
IO
DDR2 data bus
D17
BBL_TAMPER_B
BBL_TAMPER
I
BBL tamper
D18
SREG1P8_VFB
SREG1P8_VFB
IO
1.8V switching power supply feedback
D19
SREG1P2_VFB
SREG1P2_VFB
IO
1.2V switching power supply feedback
D20
NC8
NC
NC
Not in use
D21
NC3
NC
NC
Not in use
D22
USB_AVDD_1P2
USB_AVDD
P
USB analog supply-1.2V
D23
CLD9
CLD9
IO
PIF data bit 9
D24
CLD12
CLD12
IO
PIF data bit 12
D25
CLD20
CLD20
NC
Not in use
E1
VDDO_2
VDDO
P
Digital I/O supply-3.3V
E2
GPIO2
GPIO2
NC
Not in use
E3
GPIO0
12C_SDL
IO
I2C clock
E4
PLL_VDD_1P2_1
PLL_VDD
P
PLL core supply-1.2V
E5
PLL_VDD_1P2_2
PLL_VDD
P
PLL core supply-1.2V
E6
DDR_A2
DDR_A2
O
DDR2 address bus
E7
VSS_9
VSS
GND
Ground
E8
DDR_VDDO_7
DDR_VDDO
P
DDR2 I/O supply -1.8V
E9
DDR_CS_B
DDR_CS_B
O
DDR2 chip select
E10
DDR_ODT
DDR_ODT
O
DDR2 on-die termination enable
E11
VSS_10
VSS
GND
Ground
E12
DDR_DQ10
DDR_DQ10
IO
DDR2 data bus
E13
DDR_DQ11
DDR_DQ11
IO
DDR2 data bus
E14
DDR_VDDO_8
DDR_VDDO
P
DDR2 I/O supply -1.8V
E15
DDR_DQ4
DDR_DQ4
IO
DDR2 data bus
E16
VSS_11
VSS
GND
Ground
E17
BBL_VDD
BBL_VDD
P
BBL VDD supply
E18
BBL_AVSS
BBL_AVSS
GND
BLL Analog Ground
E19
SREG_AVSS
SREG_AVSS
GND
SREG Analog Ground
E20
VREG2P5_VOUT
VREG2P6_VOUT
O
2.5V regulator output
E21
USB_PLLDVDD1P2
USB_PLLDVDD
P
USB PLL Digital supply-1.2V
E22
CLD0
CLD0
IO
PIF data bit 0
E23
CLD11
CLD11
IO
PIF data bit 11
E24
CLD18
CLD18
O
PIF address bit 0
E25
CLD23
CLD23
NC
Not in use
F1
GPIO7
INT0
I
ASIC interruption input 0
F2
GPIO5
GPIO5
NC
Not in use
F3
GPIO3
DVI
O
I2C bus reference supply and reset
F4
GPIO1
12C_SDA
IO
I2C data
F5
VSS_12
VSS
GND
Ground
F21
USB_PLLAVDD_1P2
USB_PLLAVDD
P
USB PLL Analog supply-1.2V
F22
CLD2
CLD2
IO
PIF data bit 2
F23
CLD13
CLD13
IO
PIF data bit 13
F24
CLD21
CLD21
O
PIF chip select 0
F25
CLAC
CLAC
I
PIF host interrupt 1
G1
GPIO12
GPIO12
O
Test point(CTS)
G2
GPIO11
GPIO11
NC
Not in use
G3
GPIO10
ASIC(EHS)INT1
I
ASIC interruption input 1
G4
GPIO6
ASIC_RST
O
ASIC reset
G5
GPIO4
ASIC_CLK
O
Not in use
G21
USB_AVDDREF_2P5
USB_AVDDREF
P
USB analog supply-2.5V
G22
CLD4
CLD4
IO
PIF data bit 4
G23
CLD15
CLD15
IO
PIF data bit 15
G24
CLD22
CLD22
NC
Not in use
H2
GPIO16
USB0_PWRON(100mA)
NC
Not in use
H3
GPIO13
GPIO13
O
Test point(RTS)
H4
GPIO8
GPIO8
NC
Not in use
H5
GPIO9
GPIO9
NC
Not in use
H21
USB_AVSS_2
USB_AVSS_2
GND
USB Analog Ground
H22
CLD6
CLD6
IO
PIF data bit 6
H23
CLD16
CLD16
NC
Not in use
H24
NVI_A3
NVI_A3
O
NVI address bus
Pin No.
Terminal name
Function
I/Osetting
Contents Control
remark
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