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26

123

SEG1/STB1

D.O

SEG1/

KeyStrobe1

CMOS

CMOS

CMOS

CMOS

124

SEG2/STB2

D.O

SEG2/

KeyStrobe2

CMOS

CMOS

CMOS

CMOS

125

SEG3/STB3

D.O

SEG3/

KeyStrobe3

CMOS

CMOS

CMOS

CMOS

126

NC

-

-

-

-

-

-

127

NC

-

-

-

-

-

-

128

NC

-

-

-

-

-

-

Pin No.

Description

I/O

Connection

Normal

Standby

Stop

Reset

27

28

1. SCK

SCK terminal is input terminal of Serial Clock to control transmit and receipt between Master and Slave.

2. SDA

SDA terminal is input terminal, to forward the address and the mutual data between Master Device and Slave Device the
mutual.
This terminal needs the pull-up resistance external because output circuit of SDA uses Open Drain. 

3. A0, A1, A2

A0, A1, and A2 terminal is not used.

4. WP

WP terminal controls writing action. It is possible to do only reading action when high level input and it is possible to do read-
ing and writing action when low level input.

29

1

RR

A resistor to ground provides a reference current for the transmit and receive attenuators.

2

RTX

A resistor to ground determines the nominal gain of the transmit attenuator. The transmit channel gain is inversely proportional to
the RTX resistance.

3

TXI

Input to the transmit attenuator. Input resistance is nominally 5.0 kohms.

4

TXO

Output to the transmit attenuator. The TXO output signal drives the input of the transmit level detector, as well as the external cir-
cuit which drives the telephone line.

5

TLI

Input of the transmit level detector. An external resistor ac coupled to the TLI pin sets the detection level. Decreasing this resistor
increases the sensitivity to transmit channel signals.

6

TLO

Output of the transmit level detector. An external resistor and capacitor set the time the comparator will hold the system in the
transmit mode after speech ceases.

7

RLI

Input of the receive level detector. An external resistor ac coupled to the RLI pin sets the detection level. Decreasing this resistor
increases the sensitivity to receive channel signals.

8

RLO

Output of the receive level detector. An external resistor and capacitor set the time the comparator will hold the system in the
receive mode after the receive signal ceases.

9

MCI

Microphone amplifier input. Input impedance is nominally 10 kohms and the dc bias voltage is approximately equal to VB.

10

MCO

Microphone amplifier output. The mic amp gain is internally set at 34 dB (50 V/V).

11

CP1

A parallel resistor and capacitor connected between this pin and Vcc holds a voltage corresponding to the background noise level.
The transmit detector compares the CP1 voltage with the speech signal from CP2.

12

CP2

A capacitor at this pin peak detects the speech signals for comparison with the background noise level held at CP1.

13

XDI

Input to the transmit detector system. The microphone amplifier output is ac coupled to the XDI pin through an external resistor.

14

SKG

High current ground pin for the speaker amp output stage. The SKG voltage should be within 10 mV of the ground voltage at pin
22.

15

SKO

Speaker amplifier output. The SKO pin will source and sink up to 100 mA when ac coupled to the speaker. The speaker amp gain
is internally set at 34 dB (50 V/V).

16

V+

Input dc supply voltage. V+ can be powered from Tip and Ring if an ac decoupling inductor is used to prevent loading ac line sig-
nals. The required V+ voltage is 6.0 to 11 V (7.5 V nominal) at 7.0 mA.

17

AGC

A capacitor from this pin to VB stabilizes the speaker amp gain control loop, and additionally controls the attack and decay time of
this circuit. The gain control loop limits the speaker amp input to prevent clipping at SKO. The internal resistance at the AGC pin is
nominally 110 kohms.

18

CS

Digital chip select input. When at a Logic "0" (<0.7 V) the Vcc regulator is enabled. When at a Logic "1" (>1.6 V), the chip is in the
standby mode drawing 0.5 mA. An open CS pin is a Logic "0". Input impedance is nominally 140 kohms. The input voltage should
not exceed 11 V.

19

SKI

Input to the speaker amplifier. Input impedance is nominally 20 kohms.

20

Vcc

A 5.4 V regulated output which powers all circuit expect the speaker amplifier output stage. Vcc can be used to power external cir-
cuitry such as a microprocessor (3.0 mA max). A filter capacitor is required. The MC 34018 can be powered by a separate regu-
lated supply by connecting V+ and Vcc to a voltage between 4.5 V and 6.5 V while maintaining CS at a Logic "1".

21

VB

An output voltage equal to approximately Vcc/2 which serves as an analogue ground for the speakerphone system. Up to 1.5 mA
of external load current may be sourced from VB. Output impedance is 250 ohms. A filter capacitor is required.

22

Gnd

Ground pin for the IC (except the speaker amplifier).

23

XDC

Transmit detector output. A resistor and capacitor at this pin hold the system in the transmit mode during pauses between words or
phrases. When the XDC pin voltage decays to ground, the attenuators switch from the transmit mode to the idle mode. The internal
resistor at XDC is nominally 2.6 kohms.

24

VLC

Volume control input. Connecting this pin to the slider of a variable resistor provides receive mode volume control. The VLC pin
voltage should be less than or equal to VB.

25

ACF

Attenuator control filter. A capacitor connected to this pin reduces noise transients as the attenuator control switches levels of
attenuation.

26

RXO

Output of the receive attenuator. Normally this pin is ac coupled to the input of the speaker amplifier.

27

RXI

Input of the receive attenuator. Input resistance is nominally 5.0 kohms.

28

RRX

A resistor to ground determines the nominal gain of the receive attenuator. The receive channel gain is directly proportional to the
RRX resistance.