Panasonic KX-TVM200BX / KX-TVM204X / KX-TVM296X Service Manual ▷ View online
6.1.6. LAN
The LAN consists of the SMSC´s 91C113 Ethernet driver IC and a SpeedTech P52-P14-31A9 connector with a built-in
transformer. This IC driver provides 10/100base-T Ethernet integrating MAC and PHY in one chip.
transformer. This IC driver provides 10/100base-T Ethernet integrating MAC and PHY in one chip.
41
KX-TVM200BX
Network Interface
Fully integrated IEEE 802.3/802.3u-100Base-TX/10Base-T Physical Layer
Auto Negotiation: 10/100,Full / Half Duplex
LAN Interface Connector
Auto Negotiation: 10/100,Full / Half Duplex
LAN Interface Connector
6.1.7. USB
The USB employs the Mitsubishi M66591. In accordance with the USB (Universal Serial Bus) standard Rev 2.0, the M66591
is a USB peripheral controller that supports both Hi-speed and Full-speed transfer modes. The M6659 has a built-in Hi-
Speed/Full-Speed transceiver, supporting control, bulk and interrupt transfers as defined by USB standards. 3.5Kbyte-FIFO is
built in for data transfer which offers up to seven endpoints.
is a USB peripheral controller that supports both Hi-speed and Full-speed transfer modes. The M6659 has a built-in Hi-
Speed/Full-Speed transceiver, supporting control, bulk and interrupt transfers as defined by USB standards. 3.5Kbyte-FIFO is
built in for data transfer which offers up to seven endpoints.
42
KX-TVM200BX
43
KX-TVM200BX
6.1.8. Local Bus Gate
Synchronous and asynchronous buses coexist on the main board of this system. Because a synchronous bus is affected by the
signal line load capacitance and load capacitance due to the pattern of the host, in this system the synchronous bus connects
directly with the CPU acting as the primary bus, and in order to minimize the load capacitance, the board is designed taking
pattern and run lengths into consideration. Other peripheral devices connected to the asynchronous bus are separated by the
gate IC, and a gate control circuit was added to the board to open the bus as needed.
signal line load capacitance and load capacitance due to the pattern of the host, in this system the synchronous bus connects
directly with the CPU acting as the primary bus, and in order to minimize the load capacitance, the board is designed taking
pattern and run lengths into consideration. Other peripheral devices connected to the asynchronous bus are separated by the
gate IC, and a gate control circuit was added to the board to open the bus as needed.
44
KX-TVM200BX
Click on the first or last page to see other KX-TVM200BX / KX-TVM204X / KX-TVM296X service manuals if exist.