Panasonic KX-TDA0288XJ / KX-TDA0288CE (serv.man2) Service Manual / Supplement ▷ View online
13
KX-TDA0288XJ / KX-TDA0288CE
14
KX-TDA0288XJ / KX-TDA0288CE
15
KX-TDA0288XJ / KX-TDA0288CE
1.6.
BLOCK DIAGRAM
Change from the Original Service Manual Section 6
TX
+
TX
-
RX
+
RX
-
40V
GN
D
D1
5-0
A1
8-1
nWR
,nR
D
nCS
0
D1
5-0
A1
8-1
nWR
,nR
D ,n
LB
S,A
0
nCS
2
+3
.3
V
RY
n
B
Y
nR
E
S
ET
SX
SR
BRI
-I
C
(P
S
B
21
150)
+3
.3
V
n
C
S
_
BRI[0
]
+
3
.3
V
M
ODE
_0
BRI
_
R
S
T_
0
7.
68MH
z
n
IN
T
_
BRI
RJ
4
5
L
ine #
2
GN
D
2
40V
Li
n
e
In
te
rfac
e
B
lo
c
k
#1
FG
US
A
:O
n
Eu
ro
:O
ff
US
A
:O
ff
Eu
ro
:O
n
DC
_
C
O
N
T
[
D
H
W
0
(2
.048Mbp
s
)
U
H
W
0
(2
.048Mbp
s
)
Se
le
c
to
r
(8
→
1)
C
L
K
O
U
T_0
C
L
K
O
U
T_1
C
L
K
O
U
T_2
C
L
K
O
U
T_3
nC
S
[0
]
LD
[7
:0
]
LA
[1
2:
0]
nR
D
.nW
R
nC
S
I
P1
[7
:0
]
P5
[7
:0
]
P3
[7
:0
]
P4
[7
:0
]
St
at
u
s
In
d
ic
a
ti
o
n
x 8
Ju
m
p
e
r
P0
[7
:0
]
1536k
H
z
CL
K
S
e
le
c
t
e
S
AM
S
O
N
(AS
IC
)
P2
[6
:4
]
B
u
ffe
r
L
ine #
3
L
ine #
4
L
ine #
5
L
ine #
6
L
ine #
7
L
ine #
8
EC_
b
u
s
28
H
1
00 bus
11
CT
_
L
O
S
Lo
c
a
l
Re
s
e
t
nRE
SE
T
OSC
16.
384M
H
z
JT
A
G
+3
.3
V
EC_
CL
K
EC_
AD
[1
5:
0]
EC_
BE[1
:0
]
EC_
F
R
AM
E
EC_
T
R
D
Y
EC_
S
TO
P
EC_
IN
T
EC_
P
A
R
EC_
P
ERR
EC_
nR
S
T
EC_
ID
S
EL
EC_
D
ET
LD
H
W
[1
:0
]
LU
H
W
[1
:0
]
CP
[7
:0
]
HW
_
C
L
K
0
L
_N
ET
REF
CT
_N
ET
RE
nC
T_
F
R
AM
E
_A
CT
_
C
L
K
_
A
CT
_D
[7
:0
]
P2
[7
]
nR
E
SET
TC
K
TD
I
TD
O
TM
S
TR
S
T
P
LL
CLK
P2
[3
]
P2
[2
]
Ln
R
S
T
nI
R
Q
[0
]
nW
A
IT
nB
R
E
Q
nB
A
C
K
nC
S
_
[0
]_
S
D
7-0
A
1
2-0
nR
D
_
nW
R
nC
S
1
LE
D
+3
.3
V
A
L
M
(Red)
nR
S
T
nH
A
LT
LPR
S
H-1
(S
H
7020)
f=
12.
288M
H
z
nR
D
nW
R
nL
B
S
nC
S
0
nC
S
1
nC
S
2
nC
S
3
nR
E
S
nI
R
Q
1
nW
A
IT
nB
R
E
Q
nBACK
nI
R
Q
0
PB
[0
]
12.
288M
H
z
nI
R
Q
2
PB
[3
]
RX
D
TX
D
PA
[1
1]
PB
[1
0]
D15-0
A19-0
nI
N
T
_
B
R
I
RY
n
B
Y
RS-232
C
SRA
M
4Mbi
t
(2
56k
16)
Flash
4Mbi
t
(2
56k
16)
nC
S
6
+3
.3
V
D
7-0
A
7-0
NW
R
n
R
D
nI
N
T_BRI
BRI
_R
ST
_1
CL
KO
UT_1
nI
N
T_BRI
BRI
_R
ST
_2
C
LK
O
U
T_2
nI
N
T_BRI
BRI
_R
ST
_3
C
LK
O
U
T_3
nI
N
T_BRI
BRI
_
R
S
T
_
5
C
LK
O
U
T_5
nI
N
T_BRI
BRI
_
R
S
T
_
4
C
LK
O
U
T_4
CP
[0
]
C
LK
(4.
096M
Hz
)
CL
K
O
U
T
_
0
(1
53
6k
H
z)
+3
.3
V
De
c
o
d
e
r
nC
S
_
B
R
I[
7
:0
]
B
R
I_
R
S
T_7-0
M
O
D
E
_7-0
D
C
_
co
nt_
7-0
D
C
/D
CCo
n
v
er
te
r
+
15V
40V
GN
D
GN
D2
nI
N
T
_
B
R
I
nC
S
_
D
M
A
Tr
a
n
s
fo
rm
e
r
Tr
a
n
s
fo
rm
e
r
LA
10-8
PC
M
IN
PC
M
O
U
T
FS
C
DC
L
BCL
/S
C
L
K
IN
T
M
O
DE0
M
O
DE1
+3
.3
V
RT
S
CT
S
nI
R
Q
[1
]
nC
S
_
D
M
A
Su
rg
e
Ab
so
rb
er
Su
r
Ab
so
rb
er
C
L
K
O
U
T_4
C
L
K
O
U
T_5
C
L
K
O
U
T_6
C
L
K
O
U
T_7
(Green)
(Red)
nI
N
T_BRI
BR
I_
RS
T_6
C
LK
O
U
T_6
nI
N
T_BRI
BRI
_R
S
T_
7
C
LK
O
U
T_7
BRI Card Block Diagram
KX-TDA0288XJ/KX-TDA0288CE CARD BLOCK DIAGRAM
16
KX-TDA0288XJ / KX-TDA0288CE
1.7.
CHIP SELECT LOGIC
Change from the Original Service Manual Section 7.1.2.
The SH7020 has a chip select module as an internal peripheral and 8 chip select terminals are prepared outside. The area of
4Mbyte is assigned to a chip select terminal. (When DRAM is used, there is an exception partly, however it is not mentioned
here.)
Table.3 shows the chip select terminal allocation and Table.4 shows the port allocation.
4Mbyte is assigned to a chip select terminal. (When DRAM is used, there is an exception partly, however it is not mentioned
here.)
Table.3 shows the chip select terminal allocation and Table.4 shows the port allocation.
Table.3 Table of Chip Slect Terminals
Table.4 Table of Chip Slect Port allocation
Terminals
Function used
Wait Function
(Numeral is no. of
clocks.)
Remarks
CS Terminals
Individual Output
(1)
Individual Output
(2)
nCS0 (area 0)
-
-
nCS0
1+Programable or
1+Programable+WAIT
Terminals
Used for Flash memory CS.
nCS1 (area 1)
nCASH (DRAM)
-
nCS1
Read 1/Write 2 or
2+WAIT Terminals
Used for eSAMSON (ASIC) CS
nCS2 (area 2)
-
-
nCS2
1+Programable or
1+Programable+WAIT
Terminals
Used for SRAM (Basic) CS. Work
Area
Area
nCS3 (area 3)
nCASL (DRAM)
-
nCS3
Read 1/Write 2 or
2+WAIT Terminals
CS Reserve
nCS4 (area 4)
PA0 (I/O)
TIOCA0 (Timer)
nCS4
Read 1/Write 2 or
2+WAIT Terminals
2+WAIT Terminals
CS Reserve
nCS5 (area 5)
PA1 (I/O)
nRAS (DRAM)
nCS5
Read 1/Write 2 or
2+WAIT Terminals
CS Reserve
nCS6 (area 6)
PA2 (I/O)
TIOCB0 (Timer)
nCS6
1+Programable or
1+Programable+WAIT
Terminals
Used for peripheral LSI CS.
nCS7 (area 7)
PA3 (I/O)
nWAIT
nWAIT
Read 1/Write 2 or
2+WAIT Terminals
Used for Input Wait Terminals.
Chip Slect
Address
DeviceBit Wide
Assignment
Device
Bus Cycle
Remarks
nCS0
0000000h
l
0FFFFFFh
16bit
4M_Flash
2 Clock (1+Long Wait1) Port allocation of word by static bus siz-
ingBus cycle has same setting as Area 2
(nCS2).
(nCS2).
nCS1
1000000h
l
1FFFFFFh
8bit
eSAMSON
2+WAIT Terminals
Port allocation of byte by static bus sizing.
nCS2
A000000h
l
AFFFFFFh
16bit
4M_SRAM
2 Clock (1+Long Wait1) Port allocation of word by static bus siz-
ingBus cycle has same setting as Area 0
(nCS0).
(nCS0).
nCS6
6000000h
l
6FFFFFFh
8bit
BRI_IC
5 Clock (1+Long Wait4) Port allocation of byte by static bus sizing.
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