DOWNLOAD Panasonic KX-TDA0156CE Service Manual ↓ Size: 1.7 MB | Pages: 54 in PDF or view online for FREE

Model
KX-TDA0156CE
Pages
54
Size
1.7 MB
Type
PDF
Document
Service Manual
Brand
Device
PBX / 4-CHANNEL CELL STATION UNIT FOR DECT PORTABLE STATION
File
kx-tda0156ce.pdf
Date
PREV: Panasonic KX-TDA0155CE (serv.man4) Service Manual / Supplement

Panasonic KX-TDA0156CE Service Manual ▷ View online

45
KX-TDA0156CE
111 LSR-/REF
O
-
Not in use (open)
-
112 CIDIN-
O
-
Not in use (Ground)
-
113 VREF_HS/CIDOUT
O
-
Not in use (open)
-
114 MIC-
I
Pull-down(Built in) Not in use (Ground)
-
115 VREF-
O
-
Not in use (Ground)
-
116 VBUF
O
-
Voltage reference
1.5V
117 AGND
O
-
Signal ground
0.9V
118 MIC+
I
-
Not in use (Ground)
-
119 VREF+/CIDIN+
O
-
Not in use (open)
-
120 RSTn
I
-
Reset input
0:Reset
121 AD0/EXT_MEMORY
I
Pull-down(Built in) EXT_MEMORY select(Pull up)
-
122 AD1
O
-
A[0]
Address bus
123 AD2
O
-
A[1]
Address bus
124 AD3
O
-
A[2]
Address bus
125 AD4
O
-
A[3]
Address bus
126 AD5
O
-
A[4]
Address bus
127 AD6
O
-
A[5]
Address bus
128 AD7
O
-
A[6]
Address bus
46
KX-TDA0156CE
14.1.2. IC103 (FPGA)
No.
Terminal Name
I/O setting
Pull-up/down    
Processing
Contents of Control
Remark
1
INIT_DONE
O
-
Not in use(open)
For FPGA Configuration
2
ASN
-
Pull-up(Built in)
BE0n
FPGA Reserved pin
3
CLKUSR
I
-
Not in use
For FPGA Configuration
4
A6
I
-
A[6]
Address bus
5
A5
I
-
A[5]
Address bus
6
A4
I
-
A[4]
Address bus
7
A3
I
-
A[3]
Address bus
8
VCCIO
-
-
I/O Supply Voltage
3.2V
9
GND
-
-
Digital ground
-
10 A2
I
-
A[2]
Address bus
11 A1
I
-
A[1]
Address bus
12 nCSO
O
-
CS for configuration ROM
For FPGA Configuration
13 DATA0
I
-
DATA for configuration ROM
For FPGA Configuration
14 nCONFIG
I
-
Not in use
For FPGA Configuration
15 VCCA_PLL1
-
-
PLL Supply Voltage
1.5V
16 A0
I
-
A[0]
Address bus
17 RSTN
I
-
Reset Signal
0:Reset
18 GNDA_PLL1
-
-
PLL ground
-
19 GNDG_PLL1
-
-
PLL ground
-
20 nCE0
O
-
Not in use
For FPGA Configuration
21 nCE
I
-
Not in use
For FPGA Configuration
22 MSEL0
I
-
Mode Select[0] for Configuration ROM
For FPGA Configuration
23 MSEL1
I
-
Mode Select[1] for Configuration ROM
For FPGA Configuration
24 DCLK
O
-
Clock for Configuraion ROM
For FPGA Configuration
25 ASD0
O
-
DATA for Configuraion ROM
For FPGA Configuration
26 GPIO0
I/O
-
LED(G) control
General Purpose I/O
27 GPIO1
I/O
-
LED(R) control
General Purpose I/O
28 GPIO2
I/O
-
DIP SW
General Purpose I/O
29 VCCIO
-
-
I/O Supply Voltage
3.2V
30 GND
-
-
Digital ground
-
31 GPIO3
I/O
-
DIP SW
General Purpose I/O
32 GPIO4
I/O
-
DIP SW
General Purpose I/O
33 GPIO5
I/O
-
DIP SW
General Purpose I/O
34 GPIO6
I/O
-
DIP SW
General Purpose I/O
35 GPIO7
I/O
-
DIP SW
General Purpose I/O
36 GPIO8
I/O
Pull-up(Built in)
Not in use
General Purpose I/O
37 GPIO9
I/O
Pull-up(Built in)
Not in use
General Purpose I/O
38 GPIO10
I/O
Pull-up(Built in)
Not in use
General Purpose I/O
39 GPIO11
I/O
Pull-up(Built in)
Not in use
General Purpose I/O
40 GPIO12
I/O
Pull-up(Built in)
Not in use
General Purpose I/O
41 GPIO13
I/O
Pull-up(Built in)
Not in use
General Purpose I/O
42 GPIO14
I/O
Pull-up(Built in)
Not in use
General Purpose I/O
43 GND
-
-
Digital ground
-
44 VCCIO
-
-
I/O Supply Voltage
3.2V
45 GND
-
-
Digital ground
-
47
KX-TDA0156CE
46 VCCINT
-
-
Core Supply Voltage
1.5V
47 GPIO15
I/O
Pull-up(Built in)
Not in use
General Purpose I/O
48 TEST0
O
-
Not in use
Test purpose only
49 TEST1
O
Not in use
Test purpose only
50 TEST2
O
-
Not in use
Test purpose only
51 TEST3
O
-
Not in use
Test purpose only
52 HK_DET_O
O
-
Not in use
Test purpose only
53 NC53
O
-
RDI
RF RX data
54 NC54
-
Pull-up(Built in)
Not in use
-
55 NC55
-
Pull-up(Built in)
Not in use
-
56 NC56
I
-
RFSEL
RF control
57 NC57
I
-
RXDA_B
RF RX data
58 NC58
I
-
RXDA_A
RF RX data
59 NC59
O
-
SYEN_BL
RF control
60 NC60
O
-
SYEN_AL
RF control
61 NC61
I
-
SYSEL
RF control
62 NC62
I
-
LE
RF PLL control signal
63 GND
-
-
Digital ground
-
64 VCCINT
-
-
Core Supply Voltage
1.5V
65 GND
-
-
Digital ground
-
66 VCCIO
-
-
I/O Supply Voltage
3.2V
67 NC
-
Pull-up(Built in)
Not in use
FPGA Reserved pin
68 CD_PCMIN
I
Pull-up(Built in)
Not in use(open)
Test purpose only
69 CD_FSYNC
O
-
Not in use(open)
Test purpose only
70 CD_AUSEL
O
-
Not in use(open)
Test purpose only
71 CD_PCMOUT
O
-
Not in use(open)
Test purpose only
72 CD_PCMIN
O
-
Not in use(open)
Test purpose only
73 NC
-
Pull-up(Built in)
Not in use
FPGA Reserved pin
74 NC
-
Pull-up(Built in)
Not in use
FPGA Reserved pin
75 BER_CLK
O
-
Not in use
Test purpose only
76 PN9_ERR
O
-
Not in use
Test purpose only
77 NC
-
Pull-up(Built in)
Not in use
FPGA Reserved pin
78 NF0_O
O
-
Not in use(open)
-
79 NF0_I
I
-
DN_F0
8kHz Framehead from DNIC
80 GND
-
-
Digital ground
-
81 VCCIO
-
-
I/O Supply Voltage
3.2V
82 RIN_O
O
-
Not in use(open)
-
83 SIN_O
O
-
DN_DSTI
serial data to DNIC
84 SOUT_I
I
-
Not in use(pull up)
-
85 ROUT_I
I
-
DN_DSTO
serial data from DNIC
86 CONF_DONE
O
-
Configuration Conplete. to Reset Circuit
For FPGA Configuration
87 nSTATUS
I/O
-
Not in use(pull up)
For FPGA Configuration
88 TCK
I
-
Not in use(pull up)
for JTAG
89 TMS
I
-
Not in use(pull up)
for JTAG
90 TDO
O
-
Not in use
for JTAG
91 NC
-
Pull-up(Built in)
Not in use
FPGA Reserved pin
92 NC4M_I
I
-
DN_C4
Serial clock from DNIC
93 SCLK
I
-
System clock
16.384MHz
94 NC
-
Pull-up(Built in)
Not in use
FPGA Reserved pin
95 TDI
I
-
Not in use(pull up)
for JTAG
96 NC4M_O
O
-
Not in use(open)
-
97 CS3_N
O
-
Not in use(open)
Test purpose only
98 CS4_N
O
-
Not in use(open)
Test purpose only
99 NC
-
Pull-up(Built in)
Not in use
FPGA Reserved pin
100 NC
-
Pull-up(Built in)
Not in use
FPGA Reserved pin
101 GND
-
-
Digital ground
-
102 VCCIO
-
-
I/O Supply Voltage
3.2V
103 EC_DS
O
-
Not in use(open)
-
104 NC
-
Pull-up(Built in)
Not in use
FPGA Reserved pin
105 NC
-
Pull-up(Built in)
Not in use
FPGA Reserved pin
106 SF_FH
I
-
Superfame Select
0:FH, 1:SF
107 PSYNC
O
-
Superframe
1:Active
108 PCM_CLK
O
-
PCM_CK
2.048MHz
109 PCM_FSC0
O
-
PCM_F0
Framehead.8kHz
110 PCM_FSC1
O
-
PCM_F1
Frame pulse. 8kHz
111 PCM_DOUT
O
-
PCM_DN
output data to BBIC
112 PCM_DIN
I
-
PCM_UP
input data from BBIC
113 ACS2
I
-
FPGA Chip Select
0:Select
48
KX-TDA0156CE
114 NINT
O
-
Interrupt signal to IC100
0:Interrupt
115 VCCIO
-
-
I/O Supply Voltage
3.2V
116 GND
-
-
Digital ground
-
117 VCCINT
-
-
Core Supply Voltage
1.5V
118 GND
-
-
Digital ground
-
119 NA18
O
-
invert of A18
Address bus
120 D0
I/O
-
D[0]
Data bus
121 D1
I/O
-
D[1]
Data bus
122 D2
I/O
-
D[2]
Data bus
123 D3
I/O
-
D[3]
Data bus
124 D4
I/O
-
D[4]
Data bus
125 D5
I/O
-
D[5]
Data bus
126 NC
-
Pull-up(Built in)
Not in use
FPGA Reserved pin
127 NC
-
Pull-up(Built in)
Not in use
FPGA Reserved pin
128 D6
I/O
-
D[6]
Data bus
129 D7
I/O
-
D[7]
Data bus
130 GWAIT
O
-
RDY
0:Active
131 WRN
I
-
Write Enable
0:Write
132 RDN
I
-
Read Enable
0:Read
133 A23
I
-
A[22]
Address bus
134 A22
I
-
A[21]
Address bus
135 VCCINT
-
-
Core Supply Voltage
1.5V
136 GND
-
-
Digital ground
-
137 VCCIO
-
-
I/O Supply Voltage
3.2V
138 GND
-
-
Digital ground
-
139 A21
I
A[20]
Address bus
140 A20
I
A[19]
Address bus
141 A19
I
A[18]
Address bus
142 A9
I
A[9]
Address bus
143 A8
I
A[8]
Address bus
144 A7
I
A[7]
Address bus
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