Panasonic KX-NTV150NE Service Manual ▷ View online
25
KX-NTV150 Series
R0402
R0402
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
I2S
1.
I2S_TX_BCLK_io and I2S_TX_WS_io are I/O pins with
both master and slave mode
I2S_TXD_o to support
playback
2.
I2S_RX_BCLK_i and I2S_RX_WS_i are input pins with
I2S_RXD_i to support
slave mode record
3.
Please refer to HW application note for connection
examples.
TDI
nTRST
Not use
I2S share pin table:
TDO
I2S_TX_WS(B2)
I2S_TX_BCLK(B3)
I2S_MCLK(C1)
N903 ICE
I2S_TXD(B1)
I2S_RX_BCLK(A3)
LED diplay
I2S
I2S_RXD(A1)
I2S_RX_WS(A2)
LENS control
TMS
TCK
Output
Not use
Output
Output
Output
Output
Output
Output
Not use
IR_ENB
Not use
Not use
IR_FBC
PIRIS_CTRL1
PIRIS_CTRL2
AUDIO
20mil
New
SYS_SDA
SYS_SCL
AMP_EN
PERI_nRST
MICBIAS
SPK-
SPK+
I2S_TXD
I2S_RXD
I2S_WS
I2S_BCLK
I2S_RXD
I2S_WS
I2S_BCLK
I2S_MCLK
PMB
MIC-
MIC+
MICBIAS
SYS_SDA
SYS_SCL
MIC-
MIC+
I2S_TX_WS
I2S_WS
I2S_BCLK
SPK_GND
SPK
SPK-
SPK+
MICBIAS
I2S_MCLK
I2S_MCLK
I2S_TXD
AMP_EN
AEC_XTAL_OUT
AEC_XTAL_OUT
GPIO1_D17_RST
GPIO1_D17_RST
GPIO1_D17_RST
I2S_RX_BCLK
I2S_TX_BCLK
I2S_RX_WS
I2S_RXD
SPK_GND
SPK
GND
GND
GND
3V3_AUD
3V3_AUD
GND
3V3_AUD
GND
GND
GND
3V3_AUD
GND
AGND
AGND
3V3
AGND
AGND
AGND
AGND
AGND
AGND
AGND
GND
AGND
3V3_AUD
3V3
GND
GND
GND
GND
3V3
GND
GND
GND
GND
GND
SYS_SDA
SYS_SCL
AMP_EN
PERI_nRST
AMP_EN
9
GPIO1_D17_RST
U13
XC6221B322GR-G
USP-4USP-4
VIN
4
CE
3
PGND
5
VSS
2
VOUT
1
TP55
R41
100K,1%
R0402
R63
1K
R0402
J3
waferDIP1x2_125mm
Wafer 1x2_125
1
2
R85
0
R0402
R48
10K
R0402
C110
10uF,6.3V
C0402
Audio Codec
U1U
Rossini_SiP_BGA
AUDIO_LINE_OUT
C6
AUDIO_LS_OUT
B6
AUDIO_nLS_OUT
A6
AUDIO_MIC_IN
A4
AUDIO_MIC_BIAS
B4
AUDIO_LINE_IN
A5
VDDA33_AUDIO
D5
AUDIO_ADC_VREF
C4
VDDAHS33_AUDIO
D6
VSSAHS33_AUDIO
D7
VSSA33_AUDIO
E5
AUDIO_DAC_VREF
B5
AUDIO_VCM_VREF
C5
R0402
0
R157
R545
0
R0201
TP59
R0402
0
R106
C212
0.47uF,10V
C0402
R148
100
R0402
R4
10K
R0402
C213
0.47uF,10V
C0402
C211
0.47uF,10V
C0402
R107
0
R113
0
R0402
C104
33p
C0402
C304
1NF,50V
C0603
C73
1uF,10V
C0402
C239
0.1uF,6.3V
C0201
C77
1uF,10V
C0402
R46
100K,1%
R0402
R110
100
R0402
R141 100
R0402
C107
100p
C0402
C169 0.1uF,6.3V
C0201
C214
0.47uF,10V
C0402
TP18
C210
0.47uF,10V
C0402
C209
0.47uF,10V
C0402
WSCP9-TPA2011D1
U14
tpa2011d1
GND
A2
PGND
B3
VO-
A3
VO+
C3
PVDD
B2
VDD
B1
IN+
A1
IN-
C1
EN
C2
C208
0.47uF,10V
C0402
R54
100K,1%
R0402
C111
10uF,6.3V
C0402
R47
0
R0603
R79
0
R0402
C302
1NF,50V
C0603
C98
10uF,6.3V
C0402
R83
0
R0603
R84
0
R0603
C0402
C205
0.47uF,10V
TP61
R111
0
C96
10uF,6.3V
C0402
R58
100K,1%
R0402
C161
0.1uF,6.3V
C0201
R151
4.7K
R0402
TP58
C468
10pF,50V
C0402
R122
0
R0402
R38
100K,1%
R0402
R65
0
R0603
C0402
C204
0.47uF,10V
R103
R0402
R92
2.2K
R0402
R104
2.2K
R0402
C95
10uF,6.3V
C0402
R87
0
R0402
TP19
R55
100K,1%
R0402
LQFP48-FM1288
U26
FM1288
LINE_OUT_N
1
NC
2
SPK_OUT_N
3
NC
4
NC
5
NC
6
VSS_D
7
BCLK
8
FSYNC
9
TX
10
RX
11
UART_RX
12
SDA
24
SCL
23
VAD_LED
22
MUTE_OUT
21
MUTE_IN
20
VDD_D
19
VSS_D
18
GPIO
17
SCL_EE
16
SDA_EE
15
TEST2
14
UART_TX
13
PMIC_BIAS
36
VDD_A
35
PMB_VREF
34
NC
33
TEST1
32
RST#
31
PWD#
30
VSS_D
29
XTAL_OUT
28
XTAL_IN/MCLK_IN
27
VOL+
26
VOL-
25
VDD_C
37
VSS_A
38
MIC0_P
39
MIC0_N
40
MIC1_P
41
MIC1_N
42
LINE_IN_P
43
LINE_IN_N
44
VSS_A
45
VREF
46
LINE_OUT_P
47
SPK_OUT_P
48
R56
xx_0
R0603
C94
10uF,6.3V
C0402
C112
10uF,6.3V
C0402
C108
10uF,6.3V
C0402
R99
xx_10k
R0201
TP54
C215
0.47uF,10V
C0402
C162
0.1uF,6.3V
C0201
R123
0
R0402
R135
100
R0402
TP57
I2S
U1M
Rossini_SiP_BGA
I2S_MCLK_o/GPIO1_DATA[14]/UART0_TXD_o/AGPO_DATA[6]
C1
A3
B2
I2S_RX_BCLK_i/GPIO1_DATA[8]/UART0_RXD_i/AGPO_DATA[0]
I2S_RX_WS_i/GPIO1_DATA[10]/N903U_TMS_i/UART0_nCTS_i/AGPO_DATA[2]
I2S_RXD_i/GPIO1_DATA[12]/N903U_TCK_i/UART1_RXD_i/AGPO_DATA[4]
B1
I2S_TX_BCLK_io/GPIO1_DATA[9]/N903U_nTRST_i/AGPO_DATA[1]
I2S_TX_WS_io/GPIO1_DATA[11]/N903U_TDI_i/AGPO_DATA[3]
I2S_TXD_o/GPIO1_DATA[13]/N903U_TDO_o/UART1_TXD_o/AGPO_DATA[5]
C2
C3
B3
C105
33p
C0402
R2
10K
R0402
R57
100K,1%
R0402
J2
waferDIP1x2_125mm
Wafer 1x2_125
1
2
C97
33p
C0402
R140
100
R0402
C471
10pF,50V
C0402
C216
0.47uF,10V
C0402
C472
10pF,50V
C0402
KX-NTV150 Main Board No.8
26
KX-NTV150 Series
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
Reset
COL/mode pin is pulled Low -> Mii Mode
0402 (max. 400mA)
Some existed 10/100Mbps MII Ethernet PHY like IC+
IP101GA support TXER input function optionally, and
this pin can be left NC on PHY if transmit error function
is not support by MAC
Ethernet
SOC supports RGMII/MII/RMII interfaces with 3.3V voltage level only
In MII mode, TX_CLKpin provides a
continuous 25MHz clock at 100Base-TX
LED 0 and PHY Address [0]
LED 3 and PHY Address [3]
This schematic sets PHY address to 00001b.
LED and PHY address Configuration
LED0 LED3
Link 100Act
RMII/NC
GND
This pin TXER must be either floating or
connecting to
GND in RMII mode.
LED mode0
Pull high
Pull down
LED mode1
RMII mode
MII mode
*
*
*
*
--
option
RX_DV
TEST mode
Normal mode
COL/RMII
TEST
CRS
MAC_COL/RMII
MII/Pull Low
RMII/Pull High
GPIO1_D17_RST
PERI_nRST
RESET_N
REGOUT
MAC_RX_CLK
LED3
LED0/PHYAD0
MAC_RXD1
MAC_RX_DV
MAC_RXD2
MAC_RXD3
TEST_ON
MAC_MDC
MAC_CRS
MAC_RX_ER
MAC_RX_ER
MAC_RXD0
MAC_TX_ER
X1_INPUT
MAC_TXD2
MAC_TXD3
MAC_TXD3
MAC_COL/RMII
X2_OUTPUT
X2_OUTPUT
MAC_TXD0
MAC_TX_EN
MAC_TXD1
MAC_TX_CLK
MAC_MDIO
RXD+
RXD-
TXD+
TXD-
RESET_N
GTX_CLK_A
PHY_CLK_O
GTX_CLK_A
LED0/PHYAD0
LED3
MAC_RX_CLK
RX_CLK_A
TX_CLK_A
MAC_TX_CLK
MAC_COL/RMII
MAC_COL/RMII
MAC_CRS
TEST_ON
MAC_RX_DV
MAC_RX_ER
MAC_TX_ER
MAC_RXD0
MAC_RXD1
MAC_RXD3
MAC_RXD2
MAC_RX_ER
MAC_RX_DV
RX_CLK_A
MAC_CRS
MAC_COL/RMII
MAC_TXD3
MAC_TXD0
MAC_TXD2
MAC_TXD1
TX_CLK_A
MAC_TX_EN
MAC_MDC
MAC_MDIO
GPIO1_D17_RST
PERI_nRST
TXD+
TXD-
RXD+
RXD-
3V3_MII
3V3
GND
3V3_MII
3V3A_MII
3V3
3V3A_MII
GND
GND
3V3_MII
GND
GND
GND
GND
GND
3V3_MII
GND
GND
GND
GND
GND
3V3_MII
3V3_MII
GND
GPIO1_D17_RST
PERI_nRST
TXD+
[13]
RXD+
[13]
RXD-
[13]
TXD-
[13]
TP36
R32
6.19K/1%
R0603
GMAC
U1G
Rossini_SiP_BGA
GMAC_TXD[0]
G2
GMAC_TXD[1]
H1
GMAC_TXD[2]
H2
GMAC_TXD[3]
J2
GMAC_TXEN
G3
GMAC_TXCLK_o
J1
GMAC_TXCLK_i
G1
GMAC_RXD[0]
E2
GMAC_RXD[2]
F1
GMAC_RXD[1]
F2
GMAC_RXD[3]
F3
GMAC_RXER
G4
GMAC_RXDV
E3
GMAC_MDC
J4
GMAC_MD
H4
GMAC_CRS
K4
GMAC_COL
J3
GMAC_RXCLK_i
E1
GMAC_PHY_CLK_o
H3
C78
10uF,6.3V
C0402
R145
5.1K, 1%
R0402
R91
XX_1K
R0201
R127
0
R0402
C174
0.1uF,6.3V
C0201
R153
XX_5.1K, 1%
R0201
R146
5.1K, 1%
R0201
C469
xx_10pF,50V
C0402
C79
10uF,6.3V
C0402
C163
0.1uF,6.3V
C0201
C106
0.1uF,16V
C0402
R539
0
R0201
C462
22pF,50V
C0402
R88
1K
R0201
C172
0.1uF,6.3V
C0201
Y1
25MHz
CRYSTAL_25X20
1
2
3
4
TP37
C470
xx_10pF,50V
C0402
R540
xx_0
R0201
C463
22pF,50V
C0402
C144 10uF,6.3V1
C0603
R143R143
5.1K, 1%5.1K, 1%
R0201R0201
R89
1K
R0201
C467
xx_10pF,50V
C0402
TPKHZ25
R96
5.1K, 1%
R0201
R144
5.1K, 1%
R0402
R504
XX_1M
R0402
R131
0
R0402
C76
10uF,6.3V
C0402
R147
xx_5.1K, 1%
R0201
R534
30
R0201
IP101GR
U6
IP101GR
TXER/FXSD
1
X1
2
X2
3
COL/RMII
4
TXEN
5
TXD3
6
TXD2
7
TXD1
8
TXD0
9
TXCLK/50M_CLKI
10
LED0/PHY_AD0
11
LED3
12
DVDD33_IO
13
RX_CLK/50M_O
14
RXD3
15
RXD2
16
RXD1
RXD0
RXD0
17
RXDV/TPN_FIBER
18
CRS/LEDMOD
19
RXER/INTR_32
20
MDC
21
MDIO
22
TEST_ON
23
24
24
ISET
25
MDI_RN
26
MDI_RP
27
REGOUT
28
MDI_TN
29
MDI_TP
30
AVDD33
31
RESET_N
32
E-PAD
33
C466
xx_10pF,50V
C0402
R90
1K
R0201
R535
30
R0201
KX-NTV150 Main Board No.9
27
KX-NTV150 Series
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
If UART2(W6, V6) is configured as VOC_DATA[18:19], UART2
also can be swithced from I2S_RXD and I2S_TXD
When use
RS485
-->
1.
UART0_TXD
2.
UART0_RXD
3.
UART1_TXD multiplex with UARTC_0_nRTS
UART
1.
USB OTG controller supports both USB Host and USB device modes. Internal 15KOhm pull-low
resistors on DP/DM and 1.5KOhm pull-high resistor on DP save external components.
2.
5V/500mA power supply is needed for USB bus-power feature.
To avoid over-current damaging main system, a current limit fuse should be designed in bus-power
circuit.
3.
A 43.2 ohm 1% resistor should be placed between USB_REXT and Ground.
USB
USB layout routing:
1.
USB trace should keep differential characteristic impedance of 90
OHM +-10%
2.
DM/DP traces should always be matched length and no
more than 4 inches in length.
WIFI MOD
DIDO Wafer
SP
4-pin UART debug wafer:
for RS-232 cable connect to PC
1.
DI
2.
DI_GND
3.
DO
4.
DO_GND
4
1
Wireless
Engraving Area
UART2_RXD
UART2_TXD
WIFI_PW_On/Off
USB_DP
USB_DM
PERI_nRST
UART2_TXD
UART2_RXD
SOC_DO1
SOC_DI1
DO
DI
DI
SOC_DI1
SOC_DO1
DO
USB_DP
USB_DM
PERI_nRST
WIFI_PW_On/Off
GND
GND
VDDC_1V2
GND
GND
GND
3V3
GND
DO_GND
GND
DI_GND
DO_GND
DI_GND
GND
3V3
DO_GND
3V3
GND
GND
3V3
GND
GND
3V3
GND
DI_GND
3V3
WIFI_PW_On/Off
PERI_nRST
SOC_DO1
SOC_DI1
J6
WAFERSMT1X4_1MM
Wafer 1x4_1
1
2
3
4
5
6
R139
0
R0402
CP160808T-601Y,600R,1A
L100
L0603
L13
MLB-160808-0010P-N1
L0603
C200
1000pF,2KV
C1206
R112
33K,5%
R0402
D27
LMBR1100ET1G
SOD-323-L
1
2
USBUSB
U1H
Rossini_SiP_BGA
USB_IO_VBUS
B12
USB_ID
B11
USB_REXT
C12
USB_DP
A11
USB_DM
A12
VDDA33_USB
D12
VDDC12_USB
D11
VSSA33_USB
E11
VSSC12_USB
D10
VSSAC33_USB
E12
CP160808T-601Y,600R,1A
L99
L0603
C187
10uF,6.3V
C0402
D22
LMBR1100ET1G
SOD-323-L
1
2
R541
xx_0
R0201
J7
1770979
DIDO_PTSMDIP4_25MM
4
3
2
1
R78
1.5K
R0402
R543
XX_0
R0201
CP160808T-601Y,600R,1A
L103
L0603
TP11
R116
4.7K
R0402
U15
PS2801
phtosmd_ps2801_1
1
2
4
3
R266 15K,5%
R0805
C185
0.1uF,6.3V
C0201
R542
0
R0201
J8
wafer,1x4x1.25
HEADER-CWG-1X01-04A_F
1
2
3
4
F3
MF-MSMF020/60
FUSE_MF_MSMF020
1
2
R117
43.2,1%
R0402
R150
0
R0402
L14
4.7uH/1.25A/210mohm
CHOKE-PMLT25201B
C301
0.1uF,50V
C0603
UARTUART
U1J
Rossini_SiP_BGA
UART0_TXD_o/VOC_DATA[23]/AGPO_DATA[7]
UART0_RXD_i/VOC_DATA[22]/AGPO_DATA[6]
W12
V12
UART1_TXD_o/VOC_DATA[21]/UART0_nRTS_o/GPIO2_DATA[14]/AGPO_DATA[5]
UART1_RXD_i/VOC_DATA[20]/UART0_nCTS_i/GPIO2_DATA[13]/AGPO_DATA[4]
U12
U11
UART2_TXD_o/VOC_DATA[19]/UART0_nDTR_o/GPIO2_DATA[12]/AGPO_DATA[3]
UART2_RXD_i/VOC_DATA[18]/UART0_nDSR_i/GPIO2__DATA[11]/AGPO_DATA[2]
W11
V11
UART3_TXD_o/VOC_DATA[17]/UART0_nDCD_i/GPIO2_DATA[10]/AGPO_DATA[1]
UART3_RXD_i/VOC_DATA[16]/UART0_nRI_i/GPIO2_DATA[9]/AGPO_DATA[0]
W10
V10
R268 15K,5%
R0805
R149
R0603
0
R15
xx_100K
R0402
D23
LMBR1100ET1G
SOD-323-L
1
2
R544
XX_0
R0201
C84
10uF,6.3V
C0402
L12
MLB-160808-0010P-N1
L0603
R118
4.7K, 1%
R0201
U38
SY6283
DFN12x16-4L_SY6283
VI
3
GND
1
EN
2
VO
4
C83
22uF,6.3V
C0805
C184
0.1uF,6.3V
C0201
R119
4.7K, 1%
R0201
Q13
SM1110NSAC-TRG,N-MOS
SOT23_DGS
G
D
S
C186
0.1uF,6.3V
C0201
R49
1K
R0402
CP160808T-601Y,600R,1A
L98
L0603
R267 15K,5%
R0805
KX-NTV150 Main Board No.10
28
KX-NTV150 Series
5
4
D
C
VIC0 Daughter Board Connector
VIC0
Voltage level of VIC0 signal is determined by VIC0_VDDIO_SENSOR
I2CC_1_IO_SDA
I2CC_1_IO_SCL
GND
IS_1V8
xx_4.7K, 1% R129
R0201
xx_4.7K, 1% R134
R0201
C188
0.1uF,6.3V
C0201
VIC0VIC0
U1O
Rossini_SiP_BGA
VIC0_DATA[0]
K19
VIC0_DATA[1]
H16
VIC0_DATA[2]
K18
VIC0_DATA[3]
K17
VIC0_DATA[4]
K16
VIC0_DATA[5]
J16
VIC0_DATA[6]
J18
VIC0_DATA[7]
H17
J19
L18
L18
VIC0_PCLK
VIC0_HSYNC/GPIO0_DATA[22]
VIC0_VSYNC/GPIO0_DATA[21]
VIC0_VSYNC/GPIO0_DATA[21]
L19
VDDIO_SENSOR
G16
J17
H18
G17
H19
F17
G18
G19
G19
VIC0_DATA[8]
VIC0_DATA[9]
VIC0_DATA[10]
VIC0_DATA[11]
VIC0_DATA[12]/SSIC_RXD/GPIO0_DATA[23]
VIC0_DATA[13]/SSIC_nSEL[1]/GPIO0_DATA[24]
VIC0_DATA[14]/I2C1_SCL/SSIC_BCLK/GPIO0_DATA[25]
VIC0_DATA[15]/I2C1_SDA/SSIC_TXD/GPIO0_DATA[26]
VIC0_DATA[9]
VIC0_DATA[10]
VIC0_DATA[11]
VIC0_DATA[12]/SSIC_RXD/GPIO0_DATA[23]
VIC0_DATA[13]/SSIC_nSEL[1]/GPIO0_DATA[24]
VIC0_DATA[14]/I2C1_SCL/SSIC_BCLK/GPIO0_DATA[25]
VIC0_DATA[15]/I2C1_SDA/SSIC_TXD/GPIO0_DATA[26]
F18
VIC_SEN_CLK_o
F19
For 12;bit (or less) data width sensor,
VIC0_D[12:15] mux pin table:
SSIC_nSEL[1]
SSIC_RXD
SSIC_TXD
SSIC_BCLK
Voltage level of control signals (VIC0_D12,13,14,15) are determined
by VDDIO_SENSOR
by VDDIO_SENSOR
VIC0_D13_CTRL3
VIC0_D12_CTRL4
VIC0_D15_CTRL2
VIC0_D14_CTRL1
SPI Control
I2CC_1_IO_SDA
I2CC_1_IO_SCL
I2C Control
KX-NTV150 Main Board No.11
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