Panasonic KX-NS5180X-SX / KX-NS5180XSX Service Manual ▷ View online
5
KX-NS5180X/KX-NS5180SX
3 Specifications
4 General/Introduction
4.1.
General Description
KX-NS5180 (LCOT6) card is 6 analogue trunk ports with Caller ID (FSK/FSK with Call Waiting Caller ID [Visual Caller ID]/
DTMF).
This card is plluged into a free slot on NS300/500/320/520 systems and every Monitoring and/or Controlling functions are real-
ized by CPU board.
DTMF).
This card is plluged into a free slot on NS300/500/320/520 systems and every Monitoring and/or Controlling functions are real-
ized by CPU board.
Functional Block
Functional contents
Analog CO Interface
Number of Ports
6 ports
Function
DSP(DE56MF) function
• Dial pulse signal transmission function
• DTMF signal transmission function
• Polarity reversal detection function
• Bell detection function
• End-call signal detection function
• CPC signal detection function
• CODEC function
•
• DTMF signal transmission function
• Polarity reversal detection function
• Bell detection function
• End-call signal detection function
• CPC signal detection function
• CODEC function
•
/A law swiching function
• Programmable digital filter function
• Caller ID(FSK/DTMF) detection function
• CNG detection function
• Eco canceller function
• Caller ID(FSK/DTMF) detection function
• CNG detection function
• Eco canceller function
2W/4W Conversion function
Surge Protection function
Surge Protection function
Control part
CO PLD
Address decoder function
Power Failure Transfer
Supports 2 line
CO1-EXT1/CO2-EXT2
Interface Connector
CO Interface
RJ45: 3parts
MOH/EPG
Shared with CO port
6
KX-NS5180X/KX-NS5180SX
5 Technical Descriptions
5.1.
Block Diagram
EXT
PL
D
nW
R
nCS
I
A0
-A9
CA
R
D
ID
ID0-
3
n
P
LD_I
NT
D0-
D7
CLK
O
U
T
ID
0-
3
nR
E
S
E
T
0_M
LDH
W
4_M
LUH
W
4_M
LUH
W
0
A_
M
[9
:0
]
D_M
[7:0]
nW
A
IT
_M
nP
LD_
W
A
IT
D[7:0]
A
[9:0]
nR
E
A
D
n
RD_
M
nW
R
IT
E
nW
R
_M
nC
S
I
nC
S
0_
M
nC
S
1_
M
nI
N
T
nI
N
T
0_
M
n
INT
1_M
n
R
ES
ET
1_
M
TO
und
er
boar
d
TO
upp
er
boar
d
+1
5V
+3.3V
TM
S
TC
K
TD
I
TD
O
Debug
JT
A
G
Port
nW
A
IT
nRD
DA
T
A
IN
HW
C
LK
PR
O
G
R
AMN
nW
R
IT
E
H
W
_C
LK
4_M
H
W
_CLK
5_M
H
W
_CLK
6_M
CLK
IN
nH
W
_F
H
4_M
nH
W
_F
H
5_M
nH
W
_F
H
6_M
FH
IN
LDH
W
3_M
LUH
W
3_M
FH
OU
T
DA
T
A
O
U
T
DP
[0
-5
]
B
E
LL[
0-
5]
R
E
VD
ET
[0
-5
]
D
S
PG
_A
C
K
[0
-2
]
nCS
_DS
P
G
[0
-2
]
D
S
PG
_I
N
T
[0
-2
]
DE
56
M
DSP
CO
T
1
O
P
AM
P
2W
/4
W
R
ev
&
B
ell&
C
P
C
De
te
ct
or
Po
rt
#
1
T
rans
fo
rm
er
DC L
oo
p
Se
rg
e
EM
C
MO
S
SW
Be
ll L
oa
d
AI
N0
AO
U
T0
SH
U
N
T0
LOOP
0
RE
V
0
BEL
L0
T
IPC
0
RI
NGC
0
P
ort
#
2
(S
am
e as
P
or
t #1
)
P
or
t #3
(S
am
e a
s P
ort #
1)
P
ort
#
4
(S
am
e as
P
or
t #1
)
P
ort
#
5
(S
am
e as
P
or
t #1
)
LC
OT
P
ort
#
6
(S
am
e as
P
or
t #1
)
CO
R
1
CO
T
2
CO
R2
CO
T
3
CO
R3
CO
T
4
CO
R4
CO
T
5
CO
R5
CO
T
6
CO
R6
DE5
6M
DSP
A0
-A
3
D0
-D
7
A0
-A
3
D0
-D
7
A0
-A
3
D0
-D
7
X’
ta
l
13
.8
24
MH
z
CL
K
A[
3:
0]
D[
7:
0]
nR
D
nW
R
nC
S
nR
S
T
nA
C
K
LO
U
T
0
LIN
0
MI
P
MI
N
XI
N
XO
U
T
DGP
IO
4
DGPI
O2
DGP
IO
0
nIN
T
nR
S
T
DL
0
DL
1
FS
Y
N
C
SC
LK
nR
D
nW
R
nD
C
S
0
nA
C
K
0
nD
IN
T
0
nR
S
T
DH
W
1
UH
W
M
1
HW
F
H
1
HW
C
LK
1
nD
C
S
1
nD
C
S
2
LOOP
0
-5
REV0
-5
BEL
L0
-5
PC
M
H
W
PC
M
H
W
PC
M
H
W
To C
O1
-2
To C
O3
-4
To C
O5
-6
S
eri
al
ROM
Debug
DGP
IO
6
JT
A
G
S
eri
al
ROM
nA
C
K
1
nD
IN
T
1
nA
C
K
2
nD
IN
T
2
S
eri
al
ROM
DE5
6M
DSP
JT
A
G
JT
A
G
nR
S
T
_C
O
nR
S
T
nR
S
T
Debug
Debug
Debug
Debug
Debug
7
KX-NS5180X/KX-NS5180SX
5.2.
Hardware Functional Specification
5.2.1.
PLD
A PLD (Programable Logic device) is equipped on KX-NS5180, and this device has several interfacing functions as below.
5.2.2.
Dial Pulse Signal Transmission
Transmits 10pps/20pps dial pulse by a open/close action between Tip and Ring with Photo MOS relay which is controlled by DSP
(IC101).
The make width, break width and inter digit width for 10pps/20pps can be set respectively.
(IC101).
The make width, break width and inter digit width for 10pps/20pps can be set respectively.
When making DP[0-5] pin of DSP (IC101) becomes Low level, and RL101A-F turns ON. When breaking,
Function
Specification
Local Bus Interface
Bus Timing
TI CortexA8 CPU Bus Interface
Data Bus
8bit
Address Bus
10bit
Interrupt Control
External Interrupt
Up to 3
Internal Interrupt
Up to 1
CS Generate
PLD/FPGA:6 DSPG:3
DP Generate
6ch
GPIO
GPIO
CPUi/f
CPU_BUS
CO_
_
PLD
INT_CON
INT
DP_GEN
DP
CPC_DET
CPC
CS
GEN
From DSP (IC101)
+
-
-
-
+
-
+
-
REVDET[0]
VIN[0]
VOUT[0]
SHNT[0]
SHNT[0]
DP[0]
PC103A
1
2
3
4
R126A
SA100A
1
2
3
AL2
R103A
C110A
R112A
R115A
RL100A
NC
1
2
2
3
4
R102A
DG
DG
C104A
PC101A
1
2
3
4
C111A
R118A
DG
C109A
ZNR100A
+3.3V
+3.3V
R101A
+3.3V
RL101A
1
3
4
DG
DG
C112A
R106A
D104A
1
3
4
2
R117A
R125A
C113A
D109A
1
3
2
DG
SFG
R116A
D101A
+3.3V
PC100A
1
2
4
3
FG
VH1
VH1
C103A
R109A
D103A
VH1
R110A
+15V
+3.3V
TH100A
C105A
D110A
SFG
C102A
R121A
T100A
3
1
4
5
6
5
6
+3.3V
R108A
R171A
+3.3V
L100A
1
4
2
3
C138A
C139A
J100A
R122A
R124A
IC100A
4
VEE
8
VCC
Q100A
R113A
IC100A
3
2
1
IC100A
5
6
7
C107A C145A
C106A
R119A
R120A
R123A
R127A
R132A
R133A
C108A
C121A
C120A
A
8
KX-NS5180X/KX-NS5180SX
5.2.3.
Circuit For Line Acquisition
Making DP[0-5] pin of DSP (IC101) becomes Low level, and RL101A-F turns ON and the line is acquired.
It is used in common as Dial Pulse transmitting circuit.
It is used in common as Dial Pulse transmitting circuit.
DC Loop Path:
1. Ring
L100 D101 D103 D104 Q100(C-E) R112 D104 RL101 L100 Tip
2. Tip
L100 RL101 D104 R112 Q100(C-E) D104 D103 D101 L100 Ring
After line acquisition, DC and/or AC characteristics (Dynamic Range and Distortion etc) are controlled by current controll function of
DC Loop Circuit.
Also it provides the SHUNT control function for the stabilization of line power depending on the destination. Turning on PC103A-F
when transmitting pulse reduces the impedance at making, and stabilizes the line power.
DC Loop Circuit.
Also it provides the SHUNT control function for the stabilization of line power depending on the destination. Turning on PC103A-F
when transmitting pulse reduces the impedance at making, and stabilizes the line power.
5.2.4.
DTMF Signal Transmission
DTMF signal is generated by DTMF generator in the DSP device (IC101A-C).
From DSP (IC101)
+
-
-
-
+
-
+
-
REVDET[0]
VIN[0]
VOUT[0]
SHNT[0]
SHNT[0]
DP[0]
PC103A
1
2
3
4
R126A
SA100A
1
2
3
AL2
R103A
C110A
R112A
R115A
RL100A
NC
1
2
2
3
4
R102A
DG
DG
C104A
PC101A
1
2
3
4
C111A
R118A
DG
C109A
ZNR100A
+3.3V
+3.3V
R101A
+3.3V
RL101A
1
3
4
DG
DG
C112A
R106A
D104A
1
3
4
2
R117A
R125A
C113A
D109A
1
3
2
DG
SFG
R116A
D101A
+3.3V
PC100A
1
2
4
3
FG
VH1
VH1
C103A
R109A
D103A
VH1
R110A
+15V
+3.3V
TH100A
C105A
D110A
SFG
C102A
R121A
T100A
3
1
4
5
6
5
6
+3.3V
R108A
R171A
+3.3V
L100A
1
4
2
3
C138A
C139A
J100A
R122A
R124A
IC100A
4
VEE
8
VCC
Q100A
R113A
IC100A
3
2
1
IC100A
5
6
7
C107A C145A
C106A
R119A
R120A
R123A
R127A
R132A
R133A
C108A
C121A
C120A
A
From DSP (IC101)
+
-
+
-
VIN[0]
VOUT[0]
SHNT[0]
DP[0]
R126A
C110A
DG
C111A
R118A
DG
C109A
C112A
R125A
C113A
D109A
1
3
2
VH1
VH1
VH1
+15V
R121A
T100A
3
1
4
5
6
5
6
+3.3V
R171A
+3.3V
C138A
C139A
R122A
R124A
IC100A
4
VEE
8
VCC
IC100A
3
2
1
IC100A
5
6
7
C107A C145A
R119A
R120A
R123A
R127A
R132A
R133A
C108A
C121A
C120A
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