Panasonic KX-NS0131X Service Manual ▷ View online
5
KX-NS0131X
3 Specifications
3.1.
STACK-S CARD
Function
contents
Controller
• Communication between Basic shelf and Expansion shelf via Communication device.
• Followed by Command from EMPR, Control line-cards in Expansion shelf.
• Followed by Command from EMPR, Control line-cards in Expansion shelf.
CPU
SH4 32bit RISC processor made by HITACHI SH7750RF200 200MHz (16.384MHz*8) Bus
clock 65.536MHz
clock 65.536MHz
Memory
Flash-ROM
4MByte (32Mbit X 1chip, 16bit Bus)
Boot program, Store Operation, Maintenance and Diagnostic Program
Boot program, Store Operation, Maintenance and Diagnostic Program
SRAM
1MByte (32Mbit X 1chip, 16bit Bus)
Fault logging area
Battery Back Up
Fault logging area
Battery Back Up
SDRAM
16MByte (64Mbit X 2chip, 32bit Bus)
For Operation and Maintenance program Work memory
For Operation and Maintenance program Work memory
Interface between stacking
card
card
Connect to Stack-M card in NS1000 by Stacking cable.(50pin, with shield, twist pair)
Differencial signal in stacking cable
Control
Differencial signal in stacking cable
Control
• Packet Communication
Serial Bus (5Mbps)
Packet controller Made by SMSC/TMC20073
Operation clock 40MHz
Packet controller Made by SMSC/TMC20073
Operation clock 40MHz
• Control signal
Reset signal
Detect of Expansion shelf
Information number of shelf
Synchronous of ringing
Detect of Expansion shelf
Information number of shelf
Synchronous of ringing
Voice
• PCM Highway (8Mbps X 3 line)
• Highway clock (8MHz) and Frame head
• Synchronization signal of Network (like a PRI,T1)
• Highway clock (8MHz) and Frame head
• Synchronization signal of Network (like a PRI,T1)
LED display in front panel
Card Status LED on front panel Green /Red
Backboard Interface
EC Bus Interface
TDA system control bus
Synchronous 16 bit parallel bus
Synchronous 16 bit parallel bus
CT Bus Interface
128ch X 8stream Voice channel total 1024ch
In this card Select 384ch from 1024ch and transmit to Basic shelf.
In this card Select 384ch from 1024ch and transmit to Basic shelf.
LED Display on Unit Expansion Shelf Status LED(RUN,ALARM)
Etc.
Etc.
nLOS, POWERTYPE, DC_ALM, AC_ALM, nFAN_ALM, nHALT, RINGER, RING_SYNC
nSLFFAN_ALM
nSLFFAN_ALM
Power Supply
Source: +15V
generate voltage on board: +3.3V +1.2V, +1.5V
generate voltage on board: +3.3V +1.2V, +1.5V
6
KX-NS0131X
4 Technical Descriptions
4.1.
Block Diagram
nIRQ_CCLINK
CPU
SH4
IC200
FLASH
4MB
SDRAM
16MB
SRAM
1MB
ASIC
IC101
EC
CT
LE
D
A
dd/D
ata
Dri
ve
r
3.
3V
1.
2V
O
S
C16M
90pin
16.384MHz
OSC40M
RS
T
I
C
3.
3V
FPGA
IC501
CT
LVDS
SH
W
U
[2
:0
]
CP
U_
ST
A
T
US[1
:0
]
FPGA
IC
501
+1
5V
GN
D
3.
3
V
_
B
B
EC
_
C
L
K
EC
_
n
R
S
T
EC
_A
D
[15:
0]
EC
_
C
B
E
[1
:0
]
EC
_
P
A
R
EC
_
n
F
R
A
M
E
EC
_
n
T
R
DY
EC
_
n
ST
O
P
E
C
_nP
ER
R
EC
_
n
C
D
ET
EC
_
n
INT
EC
_ID
S
E
L
CT
_
N
ET
RE
F
CT
_
D
[7
:0
]
CT
_
C
8
RING
E
R
nH
A
L
T
PO
W
_
T
Y
PE
[1
:0
]
M/
nS
MA
ST
E
R
/n
S
LE
DR
UN
LE
D
A
LM
nB
A
T
T
nL
O
S
_
B
B
nSL
FFA
N
_
A
L
M
nFA
N
_
A
L
M
DC
_
A
L
M
AC
_
A
LM
RING
_
S
YN
C
SH
W
D
0_P/N
SH
W
D
1_P/N
SH
W
D
2_P/N
SH
W
U
0_P/N
SH
W
U
1_P/N
SH
W
U
2_P/N
S
_
R
ING
SY
NC
_P/
N
S_
n
RESET
_
P/N
SH
W
_
C
L
K
_
P/N
SH
W
_nFH
_P
/N
CT
_
N
ET
REF_
P
/N
C
CLI
N
K
_
P
/N
nL
O
S
_P
/N
CP
U_
ST
A
T
US0
_
P
/N
CP
U_
ST
A
T
US1
_
P
/N
nS
L
F
_PR
S
S_
ESLFI
D[1
:0
]
SH
W
D
[2
:0
]
X102
nCS4
L_nWE
L_nRD
L_nLB/UB
L_ADD[16:1]
L_DATA[15:0]
nCS0
L_nWE0
L_nRD
L_nLB/UB
L_ADD[16:1]
L_DATA[15:0]
ADD[22:17]
L_DATA[15:0]
L_nRD
L_nWE0
L_ADD[16:1]
L_nWE1
L_nWE
L_R/nW
L_
D
A
T
A
[1
5
:0
]
L_
AD
D[
1
5
:0
]
nC
S
4
nC
S
5
nR
D
L
_
nW
E
[1:
0]
nBS
n
W
AI
T
_
AS
IC
C
L
K
_
16M
nCS_CCLINK
L_nRD
nWR_CCLINK
L_ADD[5:1]
L_DATA[15:0]
CC
L
INK
_RXD
CC
L
INK
_TX
D
CC
L
INK
_TX
E
N
nDTACK
CLK_40M
X401
nDS
L_R/nW
nCS_CTSW
L_ADD[14:1]
L_DATA[15:0]
C
T
_C
8,C
T_F
R
A
M
E
CT
_
D
[7
:0
]
DATA[15:0]
nRD
nWE0
ADD[16:1]
nWE1
RD/nWR
CT
SW
_
E
N
IC
304
IC
303
IC
301,302
R
ING
_
S
YNC
ESLFI
D[1
:0
]
BM
_nR
ES
E
T
S_
ESLFI
D[1
:0
]
S_
RI
N
G
_
S
Y
N
C
L
_nW
E
L
_nR
D
L_
R/
n
W
nD
TA
CK
nW
A
IT_N
E
X
U
S
nC
S
5
nC
S
_
CC
L
IN
K
nW
R
_
CC
L
INK
nD
S
nR
DY
nI
RQ
_
A
SIC
nI
RQ
_CC
LI
NK
nD
C
_
A
L
M
SS
IC
IC
202
DATA[31:0]
ADD[15:2]
nCS2
nRAS, nCAS
RD/nWR
DQM[3:0]
CL
KI
O
DATA[31:0]
ADD[16:1]
nCS2
nRAS, nCAS
RD/nWR
DQM[3:0]
LVDS
DC
/D
C
REG
1.
5V
IC
701
IC
703
IC
706
IC
203
RI
N
G
E
R
HALT
PO
W
T
Y
P
E
MA
S
T
E
R
/n
S
M/
n
S
LED_
A
L
M
LED_
R
U
N
To C
P
U
nBA
TT
nL
O
S
_BB
nS
L
F
FA
N
_
A
L
M
n
F
A
N_
AL
M
DC
_
A
LM
AC_
AL
M
Li
-B
A
T
3.
3V
B
S
h
eet
5
S
h
eet
4
S
h
eet
4
S
h
eet
3
Sh
e
e
t 2
S
h
eet
1
REG
15V
LVDS
C
irc
-
Link
IC600
S_
n
R
ESET
BM
_nR
ES
E
T
IC
606
SH
W
_
C
L
K
, SH
W
_nFH
7
KX-NS0131X
4.2.
Hardware Functional Specification
This card is a control card for the expansion shelf.
It controls the option card contained in the expansion shelf according to the instructions of NS1000 main CPU.
On the STACK-S card are LEDs in two colors that indicate the status of the card and the bus cable connector for connecting to the
STACK-M card.
It controls the option card contained in the expansion shelf according to the instructions of NS1000 main CPU.
On the STACK-S card are LEDs in two colors that indicate the status of the card and the bus cable connector for connecting to the
STACK-M card.
ASIC Block
This block is capable of controlling the EC bus, which is a way of accessing the option card.
It also realizes TSW function by accessing the CT bus (128 timeslots).
At the same time, it is capable of controlling conference call with a range of 3 parties of 10 to 8 parties of 4.
It also realizes TSW function by accessing the CT bus (128 timeslots).
At the same time, it is capable of controlling conference call with a range of 3 parties of 10 to 8 parties of 4.
CPU Block
The CPU block consists of IC200 (CPU), X201 (Clock for Timer), IC202 (spread clock).
IC200 is the CPU that controls the expansion shelf, X201 is the clock that the CPU uses internally, and IC202 is a driver to trans-
mit the CPU operating clock from the ASIC block.
IC200 is the CPU that controls the expansion shelf, X201 is the clock that the CPU uses internally, and IC202 is a driver to trans-
mit the CPU operating clock from the ASIC block.
Memoy Block
This block consists of IC301, 302 (SDRAM), IC303 (flash ROM), IC304 (SRAM), separate the main and local buses: as well as
IC305, IC306, IC307, IC308, IC309, IC310, IC311, IC313 which separate (Logic IC).
In flash memory are stored the boot and operating programs.
SDRAM is the region in which the operating program is actually expanded and run SRAM is the region in which an error log is
temporarily stored during operation.
Access to ICs and all RAM aside from SDRAM is done through the separated local bus.
IC305, IC306, IC307, IC308, IC309, IC310, IC311, IC313 which separate (Logic IC).
In flash memory are stored the boot and operating programs.
SDRAM is the region in which the operating program is actually expanded and run SRAM is the region in which an error log is
temporarily stored during operation.
Access to ICs and all RAM aside from SDRAM is done through the separated local bus.
FPGA Block
This block consists of IC501(FPGA), IC502(Serial Flash ROM).
It is capable of exchangeing voice data between the CT Bus (1024ch) within the unit and the voice bus (384ch) from STACK-M.
Furthermore, it receives the highway clock and Frame Head from STACK-M, and outputs them to CT-BUS.
It also generates single or DTMF tones in any highway or time slot.
It is capable of exchangeing voice data between the CT Bus (1024ch) within the unit and the voice bus (384ch) from STACK-M.
Furthermore, it receives the highway clock and Frame Head from STACK-M, and outputs them to CT-BUS.
It also generates single or DTMF tones in any highway or time slot.
Commnunication Controller block
This block consists of IC600(CirkLink) and X601 (source clock 40MHz).
The CircLink is a communication controller to realize control message communication between STACK-M and STACK-S.
The CircLink chips on STACK-S card and STACK-M card are connected one-on-one basis.
Through message communication among controllers within the STACK-M card mounted in the NS1000, packet communication
with NS1000 main CPU is made possible.
LVDS(IC601) is used for actual communication.
The CircLink is a communication controller to realize control message communication between STACK-M and STACK-S.
The CircLink chips on STACK-S card and STACK-M card are connected one-on-one basis.
Through message communication among controllers within the STACK-M card mounted in the NS1000, packet communication
with NS1000 main CPU is made possible.
LVDS(IC601) is used for actual communication.
Stacking cable Connection Block
This block consists of IC601, 602, 603, 604, 605 (LVDS) and CN601 (Stacking Cable Connector).
Each control signal is converted to a differential signal through LVDS device and sent to the stacking cable.
The twisted pair cable with 50 pairs is used to connect between STACK-M card and STACK-S card.
Each control signal is converted to a differential signal through LVDS device and sent to the stacking cable.
The twisted pair cable with 50 pairs is used to connect between STACK-M card and STACK-S card.
8
KX-NS0131X
4.3.
Outline of Reset System
A reset to devices in this card is dominant in a reset from the STACK-M card, and normally it is only available for software command
reset or hardware reset using RESET IC(IC203).
Shows the reset schematic diagram.
The configration of FPGA is completed and nBSRSTOUT is released after DONE signal active.
reset or hardware reset using RESET IC(IC203).
Shows the reset schematic diagram.
The configration of FPGA is completed and nBSRSTOUT is released after DONE signal active.
4.4.
Power Supply
This card is supplied +15V power through the BackBord connector (CN103) from the power supply unit.
The power supply block is consist of following devices.
The power supply block is consist of following devices.
IC701(DC/DC converter) converting +15V into +3.3V.
IC703,IC706(Series Regulator) conveting +3.3V into +1.5V and +1.2V.
IC703,IC706(Series Regulator) conveting +3.3V into +1.5V and +1.2V.
A lithium battery is mounted in order to back up SRAM(IC304).
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