Panasonic KX-NCP1290CJ (serv.man2) Service Manual ▷ View online
33
KX-NCP1290CJ
10 Appendix Information of Schematic Diagram
Note:
1. DC voltage measurements are taken with voltmeter from the negative voltage line.
2. This schematic diagram may be modified at any time with the development of new technology.
34
KX-NCP1290CJ
11 Exploded View and Replacement Parts List
11.1. IC Data
11.1.1. IC1 (CPU)
Shows the I/O port map of CPU and Shows that of ASIC.
I/O port map of CPU
Pin
Terminals
I/O
ACT
Terminals Contents
68
nIRQ3
I
L
Reserve (interrupt)
67
nIRQ2
I
L
PRI_IC (IC301) interrupt
66
nIRQ1
I
L
Interrupt for SAMSON (ASIC) (mainly DPRAM communication
interrupt for MPR)
interrupt for MPR)
65
nIRQ0
I
L
DC power down recovery detection inversion signal of LPR
inversion signal (L:recovery)
inversion signal (L:recovery)
64
PA11
O
L
UART port for request to send [RTS0] (RS232C)
62
PA10
I
L
UART port for clear to send [CTS0] (RS232C)
61
PA9
-
-
Reserve (general-purpose I/O)
60
nBREQ
I
L
Bus request signal (bus arbitration)
58
nBACK
O
L
Bus acknowledge signal (bus arbitration)
57
nRD
O
L
Read signal (bus control)
56
nLBS
O
L
Low byte strobe signal (bus control)
55
nWR
O
L
Write signal (bus control)
54
nWAIT
O
L
Wait signal (bus control)
53
nCS6
O
L
Chip select 6 signal (bus control)
52
PA1
-
-
Reserve (Chip Select 5 signal)
51
PA0
-
-
Reserve (Chip Select 4 signal)
100
nIRQ7
-
-
Reserve (interrupt)
99
nIRQ6
-
-
Reserve (interrupt)
98
nIRQ5
-
-
Reserve (interrupt)
97
nIRQ4
-
-
Reserve (interrupt)
96
PB11
-
-
Reserve (general-purpose I/O)
95
PB10
-
-
Reserve (general-purpose I/O)
94
TxD0
O
H/L
UART port to send data [TxD0] (RS232C)
93
RxD0
I
H/L
UART port to receive data [RxD0] (RS232C)
91
PB7
-
-
Reserve (general-purpose I/O)
90
PB6
-
-
Reserve (general-purpose I/O)
89
PB5
I
L
For manufacturing test L:FManufacturing test mode
87
PB4
I
L
For card single debugging (L:Fdebug mode)
86
PB3
I
L
Flash memory busy input (L:Fbusy)
85
PB2
I
L
Reserve (general-purpose I/O)
84
PB1
I
L
Reserve (general-purpose I/O)
83
PB0
I
H
LPR inversion signal (H:Finversion)
35
KX-NCP1290CJ
11.1.2. IC2 (ASIC)
I/O port map of ASIC
Pin
Terminals
I/O
ACT
Terminals Contents
149
PO[7]
I
H/L
Reserve (Jumper setup)
148
PO[6]
I
H/L
Reserve (Jumper setup)
147
PO[5]
I
H/L
Reserve (Jumper setup)
146
PO[4]
I
H/L
Hardware version control bit2 (Jumper setup)
145
PO[3]
I
H/L
Hardware version control bit1 (Jumper setup)
144
PO[2]
I
H/L
Hardware version control bit0 (Jumper setup)
143
PO[1]
I
H/L
Number of lines info bit1 (Jumper setup)
142
PO[0]
I
H/L
Number of lines info bit0 (Jumper setup)
158
P1[7]
-
-
Reserve
157
P1[6]
-
-
Reserve
156
P1[5]
-
-
Reserve
155
P1[4]
O
L
Line Condition Display LED Green Data Link (L:Blink)
154
P1[3]
O
L
Line Condition Display LED Green Sync (L:Blink)
153
P1[2]
O
L
Line Condition Display LED Red AIS (L:Blink)
152
P1[1]
O
L
Line Condition Display LED Red RAI (L:Blink)
151
P1[0]
O
L
Line Condition Display LED Red Sync Err (L:Blink)
168
P2[7]
O
H
Line Reference Lost Signal Output (H:Reference Lost)
167
P2[6]
-
-
Reserve
166
P2[5]
-
-
Reserve
165
P2[4]
-
-
Reserve
164
P2[3]
O
L
Card Operating State Display LED Green (L:Blink)
163
P2[2]
O
L
Card Operating State Display LED Red (L:Blink)
162
P2[1]
-
-
Reserve
161
P2[0]
O
H
PRI-IC (IC301) Reset (H:Reset)
177
P3[7]
-
-
Reserve
176
P3[6]
-
-
Reserve
175
P3[5]
-
-
Reserve
174
P3[4]
-
-
Reserve
173
P3[3]
-
-
Reserve
172
P3[2]
-
-
Reserve
171
P3[1]
-
-
Reserve
170
P3[0]
O
H
Line Loopback (L:Normal Operation, H:Loopback)
199
P4[7]
-
-
Reserve
198
P4[6]
-
-
Reserve
197
P4[5]
-
-
Reserve
36
KX-NCP1290CJ
196
P4[4]
-
-
Reserve
195
P4[3]
-
-
Reserve
194
P4[2]
-
-
Reserve
193
P4[1]
-
-
Reserve
192
P4[0]
-
-
Reserve
208
P5[7]
-
-
Reserve
207
P5[6]
-
-
Reserve
206
P5[5]
-
-
Reserve
205
P5[4]
-
-
Reserve
204
P5[3]
-
-
Reserve
203
P5[2]
-
-
Reserve
202
P5[1]
-
-
Reserve
201
P5[0]
-
-
Reserve
Pin
Terminals
I/O
ACT
Terminals Contents
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