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37

This circuit consists of CCD unit, Scanning device FRIP and peripheral Op-Amp. Scanning analog signal (shading signal) which
produced by CCD PCB is amplified by OP-Amp and it is changed to binary signal (black and white) by FRIP.

1. LED Lamp Control Circuit

Port of CPU controls Q8 and Q10(ON) and 24V is supplied to LED.

2. CCD Drive Control

FCK1,2 and FSG Clock are generated by FRIP and RS is generated by PEGASUS. 
These clock drives CCD unit and CCD unit generates shading signal.

DOS

OS

RS

FCK1

FCK2

FSH

7

8

1

2

3

4

Offset Control

Q5

Q4

IC19

5

6

7

3

IC19

1

24

26

20

5

4

6

4

2

2

143

8

Differencial

Amp.

ABC

CCD

Drive

OFOUT

IC7

FRIP4

UF-585 Block

IC2

ADIN

FETD

87 VSDA

86 VSEN

85 VSCK

100 VREQ

  MACK

92

UF-595 FRIP5 PinNo. is deferent from this

  SYNC

88

  FR

89

  RS

80

S/P

PEGASUS

Shading

Correction

SRAM

IC18

DATABUS

to DRAM

CN7

CN1

LED ARRAY

24V

1

2

LED ON

Q8
Q10

CCD

TCD1208p

Shading Correction

MCLKI 16MHz

Binary Coding

Reduction

CPU

IC1

D0

0

1

2

3

6

7

8

9

10

11

12

29

30

31

32

33

34

1001

1002

1003

1004

1005

1006

1007

0

D1

D2

D3

D4

D5

D6

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D34

D35

D36

D37

D38

D39

S1

S2

S3

S4

S5

S2159

S2160

D40

D41

D42

D43

D44

D45

D46

D47

D48

D49

D50

D51

D0

D1

D2

FSG

FCK1

FCK2

FR1

DOS

OS

tINT

Dummy Signal

Dummy Signal

1 line output period

Effective
   Signal

W

B

IC19, pin1

1728 bit

Effective Scan Width

ABC Out Put Signal

38

3. Difference Amp. Circuit

CCD produces two output signal. One is OS signal which contains shading signal and noise. 
The other is DOS signal which contains noise. Differential-Amp (IC19) removes noise signal from OS signal.

4. Offset Control Circuit

Black signal voltage of Shading Signal is fixed to 0 V by differential -Amp(1C19).The offset control is decided by reference
voltage from FRIP before scanning each document.

5. ABC Circuit (Auto Background Control)

This circuit adjusts ABC signal to most suitable level of contrast, even background of document is not same level as white
level. A/D Converter in FRIP confirms the white level of shading signal from ABC Amp.(IC19). 
When the white level is too high, FRIP decreases the voltage of FETD, then reduce the shading signal Input level from ABC
amp. And when the white level is too low, FRIP increases the voltage of FETD, then increases white level. White level of
shading signal for ABC amp is controlled to keep 3V through above control.

6. A/D Converter Circuit

This circuit is in FRIP. The circuit changes shading analog signal to shading digital signal (6bit).

7. Shading Correction Circuit

This circuit consists of shading correction circuit in FRIP and shading SRAM (IC18).
This circuit corrects distortion of shading signal due to Scanning LED and optical lens.
The circuit scans the reference white on the Transmission Document Guide before the document reaches the scanning point
and writes the compensation value according to the distortion of the wave form into the SRAM. When the correction is carried
out for each page during transmission and copying.

8. Binary Coding Correction Circuit

This circuit is in FRIP. After several shading correction, the shading signal is changed to binary signal (white and black)
through binary circuit and error diffusion circuit (half tone).

9. System I/F of Scanning Data

Scanning signal which is changed to binary signal is transferred to PEGASUS. FRIP received Scanning Data Request
(VREQ)from PEGASUS and FRIP changes Transfer Enable (VSEN)to ON and transfer scanning data to PEGASUS through
VSDA line synchronizing VSCK. PEGASUS changes the scanning serial data to parallel data and transfers to Line Memory
through data bus by means of DMA.For 400dpi resolution communication, scanning data is converted from 200dpi to 400dpi
in PEGASUS (UF-595).

Scanning circuit can be checked by using Service Mode 5 (Scanning Data always out put)

1. Scanning Motor Control

CPU(IC1) controls Motor Driver (UF-595 IC26/27, UF-585 IC9/10) and drives TX motor.

2. Sensor Control

• Document & S-door Sensor

:

Output signals (APNT & SDOOR) of Photo sensor on Panel Unit are detected
by main CPU via Panel CPU (serial communication).

• Read Point Sensor

:

CPU port detects output signal (BPNT) of photo sensor on Panel Unit.

CPU

PNL RXD

SDOOR

S DOOR Sensor

Document Sensor

Read Point Sensor

APNT

A

Tr

DATI

PHA

IOA0
IOA1

DBTI

PHB

IOB0
IOB1

Tr

A

B
B

BPNT

PEGASUS

Panal

CPU

TX

Motor

Motor
Driver

Motor
Driver

39

This circuit consists of a recording picture control G/A PEGASUS, smoothing ROM and its peripheral circuit.PEGUSUS receives
print data from Line Memory (DRAM) and carries out smoothing, reduction, synchronization control, etc. Then PEGUSUS sends
print data to the LBP unit. These functions are as follows.

1. Smoothing Circuit

Current print data and compared 15 surrounding print data are output to Smoothing ROM through 16 bit line and the ROM
outputs smoothing print data. Due to this operation, distorted curved lines is smoothed.

2. Image Range Isolation Circuit

Identifies the halftone picture range and controls smoothing to eliminate blotching of 
the recording picture which has undergone error diffusion or other processing.

3. Reduction Circuit

This circuit is used to process the received data so that it fits on the recording paper.

4. Synchronization Control Circuit

This circuit is used to synchronize the output printed data with the horizontal synchronizing output signal from LBP for each
line. Within a line, It is synchronized with the dot clock signal. The dot clock signal is provided by PEGUSUS which divides the
crystal oscillator frequency from the Extend Generator Circuit (400dpi: X2 16MHz, 600dpi&300dpi: X3 36.2335MHz).

5. Laser Pulse Width Control

After smoothing, Laser Pules width is determined by software setting for print quality.

Smoothing

Process

Circuit

Timing 

Generator

Circuit

Scanning LSI

[IC17 (IC7)]

Laser Printer I/F

CPU Bus

Horizontal

Sync

Circuit

Scanning

Synchronization

Circuit

Register

(IC2)

Address

Address

Control Signal

Control Signal

System

Bus

I/F

RAM

I/F

Line

Memory

16 MHz

Crystal

Oscillator

Smoothing

Data

ROM

[IC3]

Recording Picture Process Circuit

Block Diagram

UF-595 (UF-585)

Control Signal

Address

Address

Address

Data

Data

Data Bus

40

System on FCB PCB controls LBP CPU on LPC PCB.

1. Command / Status Interface

LBP CPU replies printer condition (Status) due to request from PEGASUS (Command).

2. Printed Data Interface

Print data which is memorized in Page Memory is transferred from PEGASUS to Laser 
Diode in LSU. The transfer trigger is HSYNC (2,3 ms / line) which is generated from 
Laser Beam Detection Sensor (Horizontal Synchronized Sensor) of LSU.Transfer ratio 
due to print resolution (200dpi/300dpi/400dpi).

SCA PCB : UF-595

SCB PCB : UF-585

IC3

SMOOTHING

MASKROM

LINE MEMORY

PAGE MEMORY

DRAM

IC6 / UF-585
IC6, 7, 20 / UF-595

IC2   PEGASUS

LBP

CONTROL

UNIT

IC19   CPU

PAGE MEMORY

CONTROL

IC1   CPU

Page Memory

Control

Laser 

UNIT

LPC  PCB

IC1

Single

CHIP

CPU

LBP CPU

LBP

Mech

Control 

PRINT CONTROL SIGNAL

VIDEO SIGNAL 

(

VDO

)

PRINTER READY (PRDY)

PRINT REQUEST (PRNT)

HORIZONTAL SYNCHRONOUS (HSYNC)

PRINTER STATUS SIGNAL

COMMAND DATA BUSY (CBSY)

COMMAND DATA (CMD)

SERIAL CLOCK (SCLK)

STATUS DATA BUSY (SBSY)

STATUS DATA (STA)

PRINTER RESES (PRST)

ROM

 RAM 

Laser  I/F

VERTICAL SYNCHRONOUS (VSYNC)