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33

SEP 2005

Ver 3.0

UF-580/590/780/790

     

UF-5100/6000/6100

     

DX-600/800

1. LAN Controller (IC1)

This conforms to IEEE 802.3 Ethernet Controller. The CPU (SC PCB) bus is directly connected and the 
data interrupt is controlled by pLANINT. The 25 MHz clock is supplied by OSC 1. The LAN Controller 
for the system timing clock divides the frequency provided from OSC1. The clock signal is also 
supplied for the Manchester encoding/decoding circuit for data conversion.
The LAN Controller is a mixed signal Analog/Digital device that implements the MAC and PHY portion 
of the CSMA/CD protocol at 10 and 100Mbps.
The LAN controller contains a built in 8 KByte RAM for transmission and reception buffer.

2. EEPROM (IC2)

This memory stores the configuration registers and MAC (Media Access Control) address for the LAN 
controller. Data is transferred to LAN controller (serial transfer) when the power is turned "On". The 
MAC address for the LAN controller represents the location on the LAN.

3. Filter Transformer (T1)

A choke module transformer with a EMI filter. The output TX signal from the LAN controller is 
differentiated and transmitted on to the LAN via this module. Similarly, the input RX signal 
(differential input pair) is terminated by an externally connected 75 ohms resistor and input to the LAN
controller via this module.

4. Ethernet Interface

Provides the 10Base-T/100Base-TX Ethernet interface.

FROM 4MB/8MB

Image Memory

(IC10)

      

LANB
PCB

LANC

PCB

CPU

V850E/MA1

(IC1)

SHINE

DZAC000273

(IC3)

FROM 4MB

Program

(IC9)

      

MN86075

(IC30)

MODEM

MN195006

(I22)

D-BUS

Laser Printer

CCD PCB

Line

Line

Memory

Page

Memory

ECM

Buffer

S-DRAM 8MB

(IC7)

(2)

Transformer

(T1)

 LAN Controller

(IC1)

RJ45

LINK

ACTIVITY

INTERNET
(10Base-T/100Base-TX)

(1)

DAA

Si3021
Si3015

(IC23, 24)

34

SEP 2005

Ver 3.0

UF-580/590/780/790

     

UF-5100/6000/6100

     

DX-600/800

1. LINK LED

The LINK LED normally illuminates when the LAN cable is connected and when a link pulse is 
detected. Consequently, LED can be used to determine whether the 10Base-T/100Base-TX cable has 
become disconnected (RX side).

2. Activity LED

This LED illuminates when reception data is present on the LAN. 
(The LED also illuminates when reception data for other devices is present.)

1. LAN Transmission

a. Transfers the MMR coded data from Image Memory (FROM) to CPU (SC PCB) and converts the 

MH coded data.

b. Transfer the MH coded data of CPU (SC PCB) to SDRAM.

c. Transfer the converted text data to buffer RAM on LAN controller (LANB PCB) sequentially.

d. The transmission packet is processed by FIFO transfer to buffer RAM and then converted for 

Manchester code. Finally, they are converted for differential pair signal and transmitted to Internet.

2. LAN Reception

a. Processed received data for Manchester coded signal at LAN controller.
b. The decoded received packet goes to buffer RAM through the FIFO. The data stored in buffer RAM 

is transferred to SDRAM (SC PCB) by requests from SC PCB.

c. Decodes the Base 64 for MH coded image data at SDRAM and transfers CPU (SC PCB).

d. Inputs MMR coded data from CPU transfers Image Memory (FROM).

35

SEP 2005

Ver 3.0

UF-580/590/780/790

     

UF-5100/6000/6100

     

DX-600/800

< Check Output : If Signal is not correct, each IC
                            may be defective >

Initial Flow

Power ON

Hardware Reset

Boot Program in CPU Start

0

Is Cover Open CPU (73) and

BPNT CPU (44) is Low ?

Wait Data from PC

via Parallel I/F

Update Program

Scanning LED Lit &
Scanning LED Flashes

CPU I/O Port Set

I/O Device Reset

I/O Device Port Set

System Program (FROM) Start

SDRAM Working Area Clear

PANEL Initialize

1

UF-780/790 (xx)

UF-580/590 (xx)

Below is displayed on LCD

< Check Output : If Signal is not correct, each IC
                            may be defective >

Power

Matser

Clock

Reset

CNP6.6 3.3V -> IC1 CPU, IC3 SHINE
CNP6.7 5V -> (3) IC6 (4) 2.5V -> IC3 SHINE

5MHz -> (63) CPU (90) 50MHz
-> (103) IC3 SHINE

Reset IC2 (4) ->       -> (32) IC3 SHINE (39)
->       -> (59) IC1 CPU

XTAL

3V

0V

3.3V

0V

CPU (CS0)

IC1 CPU (107) ->        -> (26) IC9 FROM

CPU (RD)

IC1 CPU (95)   ->        -> (28) IC9 FROM

CPU (A1-21)

IC1 CPU (142-118) ->        -> 
(1-10, 16-25, 48) IC9 FROM

CPU (D0-D15)

IC1 CPU (114, 17-1) ->        -> 
(29-36, 38-45) IC9 FROM

nMDMRST

IC1 CPU (84) ->       -> (41) IC22 Modem

nFRPRST

IC1 CPU (83) ->       -> (60) IC30 FRIP

CPU (PNLTXD)

IC1 CPU (67) ->        -> CNP14.5

CPU (PNLRXD) IC1 CPU (66) ->        -> CNP14.6

CPU (PNLRST) IC1 CPU (85) ->        -> CNP14.9

5V

0V

< Check Output : If Signal is not correct, each IC
                            may be defective >

< Check Output : If Signal is not correct, each IC
                          may be defective >

...

3.3V

0V

...

N

Y

UF-580/590/
      780/790
      Only

UF-580/590/
      780/790
      Only

or

DX-800 (xx)

DX-600 (xx)

or

36

SEP 2005

Ver 3.0

UF-580/590/780/790

     

UF-5100/6000/6100

     

DX-600/800

Initial Flow 2

Back up Data Recover

Task Initialize

1

Back up Data

PARITY ERROR ?

Shipment set

System data save to FROM

Confirmation of timer, POWER OFF/ON,...

JOB Recover, if need

DISPLAY ERROR

0

SCANNER Initialize

PRINTER Initialize

# CAUTION #
Do white shading when Parity Error occurs.
(Service Mode 5-6)

SCANNER Error ?

PRINTER Error ?

N

Y

Y

DISPLAY DATE & TIME

N

23-OCT 19:14 00%

ADF OPEN     061

DOCUMENT JAM 031

CHECK PRINTER 054

(Ex.) Parameter of FROM. etc...

Task initialize for Software.

Back up data in FROM IC5 ->
Parameter, Journal,...