Panasonic UF-580 / UF-590 / UF-780 / UF-790 / UF-5100 / UF-6000 / UF-6100 / DX-600 / DX-800 Service Manual / Other ▷ View online
13
SEP 2005
Ver 3.0
UF-580/590/780/790
UF-5100/6000/6100
DX-600/800
1.1.4
Picture Signal Scanning Block
The image data read by the optical unit is input to the CCD mounted on the CCD PC Board, then
transferred to the SC PC Board after the optical information is converted into an electrical signal by the
CCD. The following shows a block diagram of the picture signal scanning circuit. This picture signal
scanning circuit consist of (1) ABC circuit, (2) shading correction circuit, (3) offset control circuit, (4) picture
signal binary coding correction circuit and (5) reducing circuit.
transferred to the SC PC Board after the optical information is converted into an electrical signal by the
CCD. The following shows a block diagram of the picture signal scanning circuit. This picture signal
scanning circuit consist of (1) ABC circuit, (2) shading correction circuit, (3) offset control circuit, (4) picture
signal binary coding correction circuit and (5) reducing circuit.
ABC Circuit
This circuit consist of IC28, IC30, C175, R288 and R285. Its function is to prevent deterioration of picture
quality due to dirt on the document or degrading of the luminous energy of the Xenon Lamp light source.
The picture signal from the CCD is amplified by IC28 and input to IC30, where it is converted from
analog to digital and the shading is corrected. When the signal exceeds +5V as the result of this
amplification and correction, capacitor C175 is charged through R288. This charging voltage lowers the
level of the picture signal input to IC28. When the picture signal voltage rises, this charge voltage
becomes higher. When the picture signal level lowers due to the background color, etc., of a transmitting
document, the voltage of the charged capacitor C175 is discharged through R285. Consequently, the
output of the ABC circuit is kept constant to maintain the picture quality, regardless of changes in the
CCD output level.
quality due to dirt on the document or degrading of the luminous energy of the Xenon Lamp light source.
The picture signal from the CCD is amplified by IC28 and input to IC30, where it is converted from
analog to digital and the shading is corrected. When the signal exceeds +5V as the result of this
amplification and correction, capacitor C175 is charged through R288. This charging voltage lowers the
level of the picture signal input to IC28. When the picture signal voltage rises, this charge voltage
becomes higher. When the picture signal level lowers due to the background color, etc., of a transmitting
document, the voltage of the charged capacitor C175 is discharged through R285. Consequently, the
output of the ABC circuit is kept constant to maintain the picture quality, regardless of changes in the
CCD output level.
W
B
1728 bit
Effective Scan Width
TCD 1208P
CCD
For UF-580/590/780/790
PD3735
For UF-580/590/780/790
DX-600/800
Differential
Amplifier
CCD PC Board
SC PC Board
CCD
Drive
Circuit
Delay
[SC]
IC30
MN86075
IC30
MN86075
IC3
DZAC000273
DZAC000273
14
SEP 2005
Ver 3.0
UF-580/590/780/790
UF-5100/6000/6100
DX-600/800
For UF-580/590/780/790, DX-600/800
For UF-5100/6000/6100
CCD Output
ABC Circuit Output
R288
C175
R285
IC28, 1
IC28, 2
32
37
19
41
39
40
IC30
Control
Circuit
OS
DOS
0V
3V
0V
-5V
+5V
Q15
Q13
ABC Circuit Output
R288
C175
R285
IC28, 1
IC28, 2
32
36
31
19
41
39
40
IC30
Vout
3V
0V
15
SEP 2005
Ver 3.0
UF-580/590/780/790
UF-5100/6000/6100
DX-600/800
Shading Correction Circuit
The Shading Correction Circuit, included in IC30, is provided to correct for reduction in LED lamp
intensity around the optical lens and LED lamp intensity distortion due to shading of each bit. This circuit
scans the white reference on the transmitting document plate immediately before the document reaches
the scanning position and writes a compensation value according to the distortion of the waveform, at
the time, into the S-RAM (IC31).When the actual picture signal is input, the circuit corrects the picture
signal shading, according to this compensation value. This shading is carried out for each page during
transmission or copy.
intensity around the optical lens and LED lamp intensity distortion due to shading of each bit. This circuit
scans the white reference on the transmitting document plate immediately before the document reaches
the scanning position and writes a compensation value according to the distortion of the waveform, at
the time, into the S-RAM (IC31).When the actual picture signal is input, the circuit corrects the picture
signal shading, according to this compensation value. This shading is carried out for each page during
transmission or copy.
Offset Control Circuit
The Offset Control Circuit consist of Q15, Q13, IC30 and IC28, and controls the black level of the CCD
output to be at 0V by using the input (IC44).
output to be at 0V by using the input (IC44).
Picture Signal Binary Coding Correction Circuit
The Picture Signal Binary Coding Correction Circuit is included in IC30. It is used to obtain a binary
coding signal which is a corrected picture and error diffused signal of a false halftone signal, which is
detected from a shaded picture signal.
coding signal which is a corrected picture and error diffused signal of a false halftone signal, which is
detected from a shaded picture signal.
16
SEP 2005
Ver 3.0
UF-580/590/780/790
UF-5100/6000/6100
DX-600/800
1.1.5
CCD Drive Clock Generator Circuit
This circuit is also contained in IC30. Its function is to generate FSG, FCK1, FCK2 and RS clock signals,
which are required for driving the CCD. These clock signals are generated by the system clock generator
circuit derived from the 4 MHz clock signal that is input to IC30. Its timing chart is shown below. The FR
clock supplied to the CCD is output from the RS of IC3. The RS clock of IC3 is derived from the FR clock of
IC30 [MN86075] generates the timing of the RS clock to drive the CCD.
which are required for driving the CCD. These clock signals are generated by the system clock generator
circuit derived from the 4 MHz clock signal that is input to IC30. Its timing chart is shown below. The FR
clock supplied to the CCD is output from the RS of IC3. The RS clock of IC3 is derived from the FR clock of
IC30 [MN86075] generates the timing of the RS clock to drive the CCD.
FCK1
FCK2
RS
FSG
CCD
FR
RS
FCK1
FCK2
FCK2
FSG
IC3
SHINE
IC30
86075
FR
UF-580/590/780/790, DX-600/800 only
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