Panasonic KX-FT76RU-B Service Manual ▷ View online
Pin No.
Pin Name
Buffer Power Supply
Description
Digital
I/O
27
XCTS/IOP33
5V
UART/Input output port selection
KIN3
I/O
28
MIDAT/IOP45
5V
Cross point IC/Input output port selection
MDMTXENB
O
29
MICLK/IOP46
5V
Cross point IC/Input output port selection
TONE1ENB
O
30
TONE1
3.3V
TONE1 (Analog output)
TONE1
31
TONE2
3.3V
TONE2 (Analog output)
TONE2
32
VOLU1
(3.3V)
Electronic volume REF for speaker
EVOL REF
33
VOLU2
(3.3V)
Electronic volume OUT for speaker
EVOL OUT
34
VOLU3
(3.3V)
Electronic volume IN for speaker
EVOL IN
35
MILAT/IOP47
5V
Cross point IC/Input output port selection
H/SRXENB
O
36
XNMI/XINT
5V
NMI/INT Input port selection
+5V
37
FMEMDO/IOP26
5V
Flash memory/Input output port selection
ALE (FLASH)
O
38
FMEMDI/IOP25
5V
Flash memory/Input output port selection
FCE (FLASH)
O
39
FMEMCLK/IOP24
5V
Flash memory/Input output port selection
R/B (FLASH)
I
40
VSS
Ground
GND
41
5V
Power supply for buffer
+5V
42
20KOSC/IOP56
5V
20kHz clock output/input output port selection
CLE (FLASH)
O
43
XWAIT/IP60
5V
Input port/XWAIT output at external CPU mode
HOOK
I
44
XHSTRD/IOP40
5V
CS*RD/input output port selection
FRD (FLASH)
O
45
XHSTWR/IOP41
5V
CS*WR/input output port selection
FWR (FLASH)
O
46
XOPRBE/
5V
OPRBE/DRAM address multiplex control/output port
SP-MUTE
O
MUX/OP53
47
ADR15/OP
5V
Address pin for debug/output port selection
H/S MUTE
O
48
ADR14/OP
5V
Address pin for debug/output port selection
OP LED
O
49
ADR13/OP
5V
Address pin for debug/output port selection
CIS ON
O
50
3.3V
Power supply for internal logic
+3.3V
51
XOUT
3.3V
24MHz crystal
XOUT
O
52
XIN
3.3V
24MHz crystal
XIN
I
53
VSS
Ground
GND
54
5V
Power supply for buffer
+5V
55
XTEST
5V
24MHz clock output
XTEST
O
56
TEST1
5V
Test pin. fixed High
+5V
57
TEST2
5V
Test pin. fixed High
+5V
58
TEST3
5V
Test pin. fixed High
+5V
59
TEST4
5V
Test pin. fixed High
+5V
60
XMDMINT
5V
MODEM interrupt
XMDMINT
O
61
XMDMCS
5V
MODEM chip selection
XMDMCS
O
62
VSS
Ground
GND
63
3.3V
Power supply for internal logic
3.3V
64
XRAS/IOP42
5V
RAS/input output port selection
XMDMRST
O
65
XCAS1/IOP43
5V
CAS of DRAM1/input output port selection
MDMCSBR
O
66
XCAS2/IOP44
5V
CAS of DRAM2/input output port selection
BELL
I
67
XRESCS2/OP71
5V
Chip selection 2/output port selection
RLY
O
68
DB3
5V
Data bus
D3
I/O
69
DB2
5V
Data bus
D2
I/O
70
DB4
5V
Data bus
D4
I/O
71
DB1
5V
Data bus
D1
I/O
72
DB5
5V
Data bus
D5
I/O
73
DB0
5V
Data bus
D0
I/O
74
DB6
5V
Data bus
D6
I/O
75
VSS
Ground
GND
76
3.3V
Power supply for internal logic
+3.3V
77
DB7
5V
Data bus
D7
I/O
78
XROMCS
5V
ROM chip selection
XROMCS
O
79
XRD
5V
Read pulse output
/RD
O
80
XWR
5V
Write pulse output
/WR
O
81
VSS
Ground
GND
82
5V
Power supply for buffer
+5V
83
ADR0
5V
Address bus
A0
O
84
ADR1
5V
Address bus
A1
O
85
ADR2
5V
Address bus
A2
O
86
ADR3
5V
Address bus
A3
O
87
ADR4
5V
Address bus (also used as DRAM address)
A4
O
88
ADR5
5V
Address bus (also used as DRAM address)
A5
O
89
ADR6
5V
Address bus (also used as DRAM address)
A6
O
90
ADR7
5V
Address bus (also used as DRAM address)
A7
O
91
ADR8
5V
Address bus
A8
O
92
ADR9
5V
Address bus
A9
O
105
KX-FT76RU-B
Pin No.
Pin Name
Buffer Power Supply
Description
Digital
I/O
93
ADR10
5V
Address bus
A10
O
94
ADR11
5V
Address bus
A11
O
95
ADR12
5V
Address bus (SRAM can´t be used.)
A12
O
96
VSS
Ground
GND
97
5V
Power supply for buffer
+5V
98
RBA0
5V
Bank address (also used as DRAM address)
A13
O
99
RBA1
5V
Bank address (also used as DRAM address)
A14
O
100
RBA2
5V
Bank address (also used as DRAM address)
A15
O
101
RBA3
5V
Bank address (also used as DRAM address)
A16
O
102
RBA4
5V
Bank address (also used as DRAM address)
A17
O
103
RBA5/OP
5V
Bank address (also used as DRAM address)/output
port selection
port selection
A18
O
104
RBA6/IOP96
5V
Bank address/Input output port selection
PAPER
I
105
STB1
5V
Thermal head strobe 1
STB1
O
106
STB2
5V
Thermal head strobe 2
STB2
O
107
STB3
5V
Thermal head strobe 3
OPEN
108
XRESET
5V
Reset input for internal digital circuit
XRESET
I
109
XORESET
5V
No chattering RESET (Noise reduction of XRESET )
XORESET
O
110
5V
Power supply for buffer
+5V
111
VSS
Ground
GND
112
XRESETI
5V
Input the comparator output for reset.
XRESETI
I
113
XWDERR
5V
Watch dog error
XWDERR
OD
114
THDAT
5V
Thermal head data
TH DATA
O
115
THCLK
5V
Thermal head clock
TH CLK
O
116
3.3V
Power supply for internal logic
+3.3V
117
VSS
Ground
GND
118
THLAT
5V
Thermal head latch
TH LAT
O
119
STBNP
5V
Input port
MOTOR POS.
I
120
RM0/IOP00
5V
Motor control/input output selection
T5
O
121
RM1/IOP01
5V
Motor control/input output selection
T4
O
122
RM2/IOP02
5V
Motor control/input output selection
T3
O
123
RM3/IOP03
5V
Motor control/input output selection
T2
O
124
RXE/IP04
5V
Motor control/input selection
T0
O
125
TM0/IOP10
5V
Motor control/input output selection
KSTART
O
126
5V
Power supply for buffer
+5V
127
VSS
Ground
GND
128
TM1/IOP11
5V
Motor control/input output selection
LED ON
O
129
TM2/IOP12
5V
Motor control/input output selection
THON
O
130
TM3/IOP13
5V
Motor control/input output selection
KTXD
O
131
TXE/IP14
5V
Motor control/input selection
KRXD
I
132
KSTART
5V
Operation panel I/F
KSCLK
O
133
KLATCH
5V
Operation panel I/F (also used as output port)
KLATCH
O
134
KSCLK
5V
Operation panel I/F
OPEN
135
KTXD
5V
Operation panel I/F
OPEN
136
KRXD
5V
Operation panel I/F
GND
137
ADSEL1
5V
AIN2 control 1
ADSEL1
O/Z
138
VSSC
Ground for analog video processing
GND
139
VDDC
Power supply for analog video processing
+3.3V
140
VSSA
Ground for analog video processing
GND
141
VDDA
Power supply for analog video processing
+3.3V
142
VREFB
Analog
A/D Reference -
VREFB
143
VCL
Analog
Clamp level
VCL
144
VREFT
Analog
A/D Reference +
OPEN
106
KX-FT76RU-B
5.3.3. ROM (IC2)
This 512 KB ROM (OTPROM or MASKROM) has 32 KB of common area and bank area (BK4~BK 63).
The capacity of each bank is 8 KB.
The addresses of the common area are from 0000H to 7FFFH, and addresses 8000H to 9FFFH are for the bank area.
5.3.4. RAM (IC4)
This 32 KB RAM has 8 KB of common area and bank area (BK0, BK1).
The capacity of each bank is 12 KB.
The addresses of the common area are from D000H to EFFFH, and addresses A000H to CFFFH are for the bank area.
The addresses of the common area are from D000H to EFFFH, and addresses A000H to CFFFH are for the bank area.
5.3.5. Reset Circuit
The output from pin 1 of the Reset IC (IC3) resets the gate array (IC1).
1. During a power surge, a positive reset pulse of 50 msec or more is gerated and the system is reset completely.
This is done to prevent partial resetting and system runaway during a power fluctuation.
2. When pin 1 of IC3 becomes low, it will prohibit the RAM (IC4) from changing data.
The RAM (IC4) will go into the backup mode, when it is backed up by a lithium battery.
3. The watch dog timer, built-in the gate array (IC1), is initialized about every 1.5 ms.
When a watch dog error occurs, pin 113 of the gate array (IC1) becomes low.
The terminal of the WDERR signal is connected to the reset line so the WDERR signal works as the reset signal.
The terminal of the WDERR signal is connected to the reset line so the WDERR signal works as the reset signal.
107
KX-FT76RU-B
5.3.6. SRAM and RTC BACK UP CIRCUIT
1. Function
This unit has a lithium battery (BAT1) which works for the RAM (IC4) and Real Time Clock (RTC, Integrated into ASIC:IC1).
The user parameter for auto dial numbers, the transmission ID, the system setup date and so on are stored in the RAM (IC4).
The RTC continues functioning, even when the power switch is OFF, backed up by a lithium battery.
The user parameter for auto dial numbers, the transmission ID, the system setup date and so on are stored in the RAM (IC4).
The RTC continues functioning, even when the power switch is OFF, backed up by a lithium battery.
2. Circuit Operation
When the power is turned ON, power is supplied RAM (IC4) and RTC (IC1).
At this time, the voltage at pin 28 of RAM is +5V and pin 7 of RTC (IC1) is +3.3V. When the power is turned OFF, the battery
supplies the power to RAM and RTC through J1, R16, D1 or DA1. At that time, the voltage at pin 28 of RAM and pin 7 of IC1
are about +2.5V. When the power is OFF and the +5V and +3.3V voltages decrease, IC3 detects them and LOW is input to pin
112 of IC1. Pin 109 of IC1 outputs the reset signals. Pin 28 of RAM (IC4) and pin 11 of IC1 become low, then RAM and RTC
(IC1) go into the back up mode, when the power consumption is lower.
At this time, the voltage at pin 28 of RAM is +5V and pin 7 of RTC (IC1) is +3.3V. When the power is turned OFF, the battery
supplies the power to RAM and RTC through J1, R16, D1 or DA1. At that time, the voltage at pin 28 of RAM and pin 7 of IC1
are about +2.5V. When the power is OFF and the +5V and +3.3V voltages decrease, IC3 detects them and LOW is input to pin
112 of IC1. Pin 109 of IC1 outputs the reset signals. Pin 28 of RAM (IC4) and pin 11 of IC1 become low, then RAM and RTC
(IC1) go into the back up mode, when the power consumption is lower.
108
KX-FT76RU-B
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