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The camera features an optical zoom that allows you to magnify images by up to 21

× (10 levels of zoom) and a digital zoom that

allows you to further magnify images by up to 2

× (2 levels of zoom), for a total zoom range of 42×.

Focusing can be adjusted manually or automatically, allowing you to control the camera’s focus to suit your needs.

Camera images can be monitored from a PC, both on-site and over the Internet. You can even use your mobile phone to view
still images when you’re out of the house.

Live camera images can be viewed and buffered (i.e., stored in memory) in both MPEG-4 and JPEG (MJPEG) formats, allowing
you to select the video format that best suits your needs.

The camera’s motion detection feature allows you to buffer or transfer camera images when the camera detects motion in the
camera image.

Camera images can be automatically buffered at specific times, when the camera’s external sensors (customer-provided) are
triggered, or when the camera detects motion. You can program the camera to buffer these camera images, and then you can
play back these images later while accessing the camera or save them to your PC. You can also program the camera to transfer
images by E-mail or upload them to an FTP or HTTP server as they are being buffered.

Camera images can be recorded to an optional SD memory card in addition to the camera’s internal memory.
The camera supports Panasonic SD memory cards from 64 MB to 2 GB in capacity, allowing you to store thousands of camera
images on a single card.

When connecting the camera to a UPnP™ compatible router, the camera’s network settings can be automatically configured,
making setup quick and easy. For more information, see Operating Instructions.

After registering your camera with the Viewnetcam.com service, you can access the camera while away from home using an
easy to remember Internet address of your choosing, such as ***. viewnetcam.com. For more information, see Operating
Instructions.

All camera pages can be displayed in English, French, German, Italian, Spanish, Russian, Simplified Chinese, and Japanese.
The most commonly used camera pages can be displayed in Korean.

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• The IC102 is a system LSI for a network camera containing the CPU
• The power supply voltages are +3.3V (I/O) and +1.2V(inside).
• The CPU is performs mainly hardware control, TCP/IP protocol processing and applications such as http and FTP.
• The clock setting is 27MHz, 48MHz, 57MHz and 108MHz by inside, which multiphy 48MHz oscillation in the X101 by PLL.
• There are two types of external bus: the General-purpose bus and the bus for SDRAM only.
• The General bus is connected to a Flash Memory for program storage.
• The capacity of the Flash Memory (IC104) is 64Mbit (2Mx16bit); the program, the setting information for the network camera and

the MAC address are stored.

• Two SDRAMs (IC103/106) of 128Mbit (8Mx16bit) are used, which are connected to CPU with bus width of 32bit, and are avail-

able for CPU processing work, storage of communication data, and storage of audio/image data.

• The RESET IC (IC101) monitors the power supply voltage, detects the rising edge of +3.3V and generates the Hardware Reset

Signal.

• IC110 is RTC (Real Time Clock), and is used for time setting of image transfer, etc. This is backed up by a lithium battery on the

IO board (BAT101) even at the time of power OFF. I2C Bus is used as I/F with CPU.

• There is an RTC block inside IC102, and this inside RTC block operates during the existence of electricity by importing the clock

data from IC110 at the time of power ON.

• IC102 is equipped with the GPIO terminal, which is used for motor control, IO terminal control, etc.
• An SD memory card control block is included on IC102, and used by connecting an SD card slot (CN101).
• There is a green LED (LED101) near the SD card slot, and it lights while the SD card is being accessed.
• When LED(LED101) is turned off by pressing the FUNCTION switch(SW103) and the access to the SD card, the SD card can be

safely pulled out.

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• IC701 is a CCD image sensor of approximately 320 thousand pixels, which outputs the image signal (CCD_OUT) of an VGA

(640x480) size.

• IC803: This IC is to remove noise in the CCD_OUT signal, adjust the gain and output the 10-bit data (AFE_D[9:0]). 

The pixel clock (PCLK: 12.2727MHz) and CCD_Hdrive signal are output based on the timing of the synchronizing signals
(HD_AFE and VD_AFE) that are generated by the CLOCK signal from the IC804.The synchronizing signals (HD_AFE and
VD_AFE) are output from the CPU (IC102) on the CPU board. 
The pixel clock (PCLK) and 10-bit data (AFE_D [9:0]) that are output from the IC803 are entered in the LVDS Transmitter IC
on IC806, and after being parallel-serial converted, they are converted into the two-wire differential signals. Then the signals
are transmitted to the LVDS Receiver IC (IC121) on the CPU board. In the LVDS Receiver IC (IC121), the signals are then
serial-parallel converted to recover the pixel clock and the 10-bit data, which are entered into the CPU (IC102). (Refer to Fig.
1.) 

• Frequency of the IC803 clock (CLOCK signal) is 24.5454MHz and the clock signal is generated in the IC804 based on timing of

the crystal oscillator (X801).

• The IC803 is controlled by the serial signals (CS_AFE, SDI, and SCL) in the CPU (IC102).

The SDI and SCL signals in the serial signals are shared and used in the DA converter (IC903) and the motor driver (IC901)
that are mounted on the LENS board. (Refer to Fig. 2.) 

• Hard reset (RESET) of IC803 is controlled by GPIO of IC102 on the CPU board.
• IC802 receives the V drive timing signals (Vdrive: CH1, CH2, and XV1-XV4) from the IC803, and outputs the IC701 (CCD) drive

V drive signal (CCD_Vdrive: V1-V4).

• The power supplies used in the camera unit are generated +15V and -5.5V in the IC801 and +3.3V from the +5.7V power sup-

plied from the TILT board. 

The power supplies are generated +15V and -5.5V in the IC801 and +3.3V and -0.4V in the IC809 for driving the CCD.

Figure 1 Video Signal Transmission via LVDS

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Figure 2 Sharing of Serial Signals (SDI and SCL)

• Pixel clock and 10-bit RAW data that are output from the IC803 are transmitted to the LVDS Receiver IC (IC121) on the CPU

board via the LVDS Transmitter. In the LVDS Receiver IC (IC121), they are serial-parallel converted to recover the pixel clock
(CAM_CLK) and 10-bit RAW data (CAMD [11:2]), and the recovered pixel clock and 10-bit RAW data are entered into the CPU
(IC102). 

• In the VIDEO SIGNAL Processor unit that is imbedded in IC102, the RAW data is subjected to such signal processing as OB

clamping, white balancing, and É¡ processing, then the RAW data is temporary recorded in the external SDRAM. The RAW data
is subjected to the three-step processing that is composed of pixel correction, YC generation and scaling, and the data after the
processing is recorded in the same external SDRAM as the image data. 

• The synchronizing signals (CCDHD and CCDVD) and AFE control serial signals (AFE_LD, SDI, and SCL) from the CPU

(IC102), are sent to the AFE IC (IC803) on the VIDEO board via CN102.

Camera has 21 X optical zoom lens. This lens unit has the ZOOM lens drive motor, the FOCUS lens drive motor, the IRIS unit,
and the position detection circuit for ZOOM and FOCUS lens, respectively. These components are controlled from the CPU
(IC102) on the CPU board.