Panasonic CQ-C3401W Service Manual ▷ View online
9.1. Main Block
IC601 : YESAM282
Pin
No.
Port
Description
I/O
(V)
FM AM CD
1
(NC)
-
-
-
-
-
2
VSM
Radio signal strength
I
0
0
0
3
SD/ST
Radio station detect
I
0.3
0
0.8
4
AVSS
Ground
-
0
0
0
5
SCL
Audio control serial clock
O
4.9
4.9
4.9
6
SDA
Audio control data
O
4.9
4.9
4.9
7
AVREF
(Conecting to +5V)
-
4.9
4.9
4.9
8
CD SO
CD data output
I
2.1
2.3
1.7
9
CD SI
CD data input
O
0
0
3.3
10 CD SCK
CD clock
O
4.7
4.7
4.7
11 CDC DATA
CD changer data
I
0
0
0
12 XM-RX SI (NC)
-
-
-
-
-
13 CDC CLK
CD changer clock
I
0
0
0
14 CDC REM
CD changer remote
O
4.8
4.8
4.8
15 BZ OUT
Buzzer out
O
4.4
4.4
4.4
16 LCD DO
LCD data
I
4.8
4.8
4.8
17 LCD DI
LCD data
O
4.7
4.7
4.7
18 LCD CLK
LCD Clock
O
4.8
4.8
4.8
19 CD MUTE
CD mute
I
0
0
4.8
20 CD RST
CD reset
O
4.8
4.8
4.8
21 CD STB
CD strobe
I
3.7
3.7
3.7
22 CDC SENS
(NC)
-
-
-
-
-
23 PLL DO
PLL data
I
4.9
4.9
4.9
24 PLL CLK
PLL data clock
O
4.8
4.8
4.8
25 PLL DI
PLL data
O
0
0
0
26 PLL CE
PLL chip select
O
0
0
0
27 (NC)
-
-
-
-
-
28 (NC)
-
-
-
-
-
29 (NC)
-
-
-
-
-
30 (NC)
-
-
-
-
-
31 (NC)
-
-
-
-
-
32 (NC)
-
-
-
-
-
33 VSS1
Ground
-
0
0
0
34 RDS DATA
(NC)
-
-
-
-
-
35 S-LED
LED control
O
0
0
0
36 LCD CE
LCD chip enable
O
0
0
0
37 LCD 5V CNT
Display 5V control
O
0
0
0
38 EJ ILL
LED control (EJ/ILL)
O
4.8
4.8
4.8
39 OP/CL
Panel open/close detect
I
4.9
4.9
4.9
40 (NC)
-
-
-
-
-
41 EJECT
EJECT switch
I
4.9
4.9
4.9
42 ROTARY 1
Rotary encoder input 1
I
4.8
4.8
4.8
43 ROTARY 2
Rotary encoder input 2
I
4.7
4.7
4.7
44 (NC)
-
-
-
-
-
45 (NC)
-
-
-
-
-
46 PANEL
Panel detection
I
4.6
4.6
4.6
47 STBY
Power IC stundby control
O
4.8
4.8
4.8
48 EEPROM CE
(Not Used)
-
-
-
-
49 EEPROM SK
(NC)
-
-
-
-
-
50 EEPROM DI
(NC)
-
-
-
-
-
51 EEPROM DO
(Not Used)
-
-
-
-
52 CDC1/2 (NC)
-
-
-
-
-
53 INV CNT
Illumination control
O
4.8
4.8
4.8
54 AMP CNT
Amp power control
O
4.8
4.8
4.8
55 ANT CNT
Antenna power control
O
4.8
4.8
4.8
56 EXT.MUTE
External mute
O
4.8
4.8
4.8
57 MAIN CNT
Main power control
O
4.8
4.8
4.8
Pin
No.
Port
Description
I/O
(V)
FM
AM CD
58 AMP MUTE
Amp mute control
O
4.8
4.8
4.8
59 AF MUTE
AF mute control
O
4.8
4.8
4.8
60 RESET
Reset
I
4.8
4.8
4.8
61 RDS CLK (NC)
-
-
-
-
-
62 (NC)
-
-
-
-
-
63 (NC)
-
-
-
-
-
64 RM DATA
Remote control data
I
4.8
4.8
4.8
65 BATT
Battery voltage detection
I
4.5
4.5
4.5
66 CDC STB/
XM DET
CD Changer strobe/ XM
receiver detection
receiver detection
I
4.8
4.8
4.8
67 VSS0
Ground
-
0
0
0
68 VDD1
+5V power supply
-
4.8
4.8
4.8
69 X2
Crystal oscillator
-
2.9
2.9
2.9
70 X1
Crystal oscillator
-
2.3
2.3
2.3
71 TEST
(TEST terminal)
-
0
0
0
72 XT2
Crystal oscillator
-
2.7
2.7
2.7
73 XT1
Crystal oscillator
-
2
2
2
74 VDD0
+5V power supply
-
4.9
4.9
4.9
75 AVDD
+5V power supply
-
4.8
4.8
4.8
76 INI A
Mode setting A
I
3.2
3.2
3.2
77 INI B
Mode setting B
I
0
0
0
78 ACC
ACC detection
I
4.9
4.9
4.9
79 (NC)
(Connecting to ground)
-
0
0
0
80 LEVEL
(Connecting to ground)
-
0
0
0
9.2. Display Block
IC901 : YEAMLC75854T
Pin
No.
Port
Description
I/O
(V)
1-39 SEG1-39
LCD segment data
O
2.5
40-43 COM1-4
LCD common
O
2.5
44,45 SEG40,41
Not used
-
-
46-49 KS3-6
Key scan
O
5.0
50-54 Kl1-5
Key data
I
0
55
TEST
(Connecting to ground)
-
0
56
VDD
+5V power supply
-
5.0
57
VDD1
VDD1 filter terminal
-
3.3
58
VDD2
VDD2 filter terminal
-
1.7
59
VSS
Ground
-
0
60
OSC
Oscillator terminal
-
3.9
61
DO
Key data output
O
5.0
62
CE
LCD driver chip enable
I
0
63
CLK
LCD clock
I
4.9
64
DI
LCD data
I
4.9
9 TERMINALS DESCRIPTION
5
CQ-C3401W
9.3. CD Servo Block
IC401 : YESAM275
Pin
No.
Port
Descriptions
I/O
(V)
1
CVSS1
GND
-
0
2
-
-
-
-
3
CVSS2
GND
-
0
4
DVDD1
I/O system (3.3V) power supply
-
3.3
5
A10
Address bus of FLASH ROM
O
0
6
-
-
-
-
7
A11
Address bus of FLASH ROM
O
3.3
8
A12
O
3.3
9
A13
O
3.3
10
A14
O
3.3
11
A15
O
3.3
12
/CVDD1
CORE CPU system (1.6V) power
supply
supply
-
1.6
13
-
-
-
-
14
DVSS1
GND
-
0
15
CVSS3
GND
-
0
16
/CVDD2
I/O system (3.3V) power supply
-
1.6
17
-
-
-
-
18
-
-
-
-
19
READY
-
-
3.3
20
/PS
FLASH ROM selection signal
O
3.3
21
-
-
-
-
22
-
-
-
-
23
R/W
Lead/light signal to FLASH ROM
O
3.3
24
/MSTRB
Memory access signal
O
3.3
25
-
-
-
-
26
/MSC
-
-
3.3
27
MUTE
Mute signal output (H:Mute on)
O
0
28
-
-
-
-
29
-
-
-
-
30
/HOLD
-
-
3.3
31
BIO
SUBO input
I
0
32
MP/MC
Operation mode setting (external
pull-up)
pull-up)
I
3.3
33
DVDD2
I/O system (3.3V) power supply
-
3.3
34
CVSS4
GND
-
0
35
BD R1
GND
I
0
36
-
-
-
-
37
CVSS5
GND
-
0
38
-
-
-
-
39
-
-
-
-
40
DVSS2
GND
-
0
41
CLK C M AUDIO bit clock input
I
1.6
42
SCK
Clock input
I
3.3
43
LRCK C
M
M
AUDIO L/R identifying signal input
I
1.6
44
CDFS
Serial frame sink signal input
I
2.6
45
DATA
CM
CM
AUDIO serial data input
I
1.6
46
-
-
-
-
47
SI
Serial data input
I
0
48
CLK M C AUDIO bit clock output
O
1.6
49
SCK
Clock input
I
3.3
50
CVSS6
GND
-
0
51
-
-
-
-
52
CVDD3
CORE CPU system (1.6V) power
supply
supply
-
1.6
53
LRCK M
C
C
AUDIO L/R identifying signal output
O
1.6
54
CDFS
Serial frame sink signal input
I
2.4
55
-
-
-
-
56
DVDD3
I/O system (3.3V) power supply
-
3.3
57
DVSS3
GND
-
0
Pin
No.
Port
Descriptions
I/O
(V)
58
REST
SW
SW
Mechanics deck REST SW input
I
3.3
59
DATA M
C
C
AUDIO serial data output
O
1.6
60
SO
Serial data output
O
1.2
61
-
-
-
-
62
-
-
-
-
63
/NMI
-
-
3.3
64
/INT0
-
-
3.3
65
/INT1
-
-
3.3
66
BLKCK
Subcode block clock pulse input
I
0
67
/INT3
-
-
3.3
68
CV DD4
CORE CPU system (1.6V) power
supply
supply
-
1.6
69
SW1
Mechanics deck SW1 input
I
0
70
CVSS7
GND
-
0
71
MCLK
Clock output (To Servo DSP)
O
3.3
72
DVSS4
GND
-
0
73
MLD
Command load signal output (To
Servo DSP)
Servo DSP)
I
3.3
74
MDATA
Command data output (To Servo
DSP)
DSP)
O
3.3
75
DVDD4
I/O system (3.3V) power supply
-
3.3
76
DVSS5
GND
-
0
77
CLK MD1 Clock mode setting (L fixation)
I
0
78
CLK MD2 Clock mode setting (H fixation)
I
3.3
79
CLK MD3 Clock mode setting (L fixation)
I
-
80
-
-
-
-
81
SW2
Mechanics deck SW2 input
I
0
82
-
-
-
-
83
EMU0
-
-
0
84
EMU/OF
F
F
-
-
3.3
85
TDO
-
-
3.3
86
TDI
-
-
0
87
/TRST
-
-
3.3
88
TCK
-
-
0
89
TMS
-
-
3.3
90
CVSS8
GND
-
3.3
91
CVDD5
CORE CPU system (1.6V) power
supply
supply
-
0
92
HPIENA
GND
I
1.6
93
DVSS6
GND
-
0
94
-
-
-
-
95
CLKENA Oscillation output Cainabl signal
O
3.3
96
X1
Crystal Connection
O
0
97
X2/CLKIN Crystal Connection
I
0
98
RS
Reset signal input
I
1
99
D0
Data base of FLASH ROM
I/O
3.4
100
D1
I/O
0
101
D2
I/O
0
102
D3
I/O
0
103
D4
I/O
0
104
D5
I/O
0
105
A16
Address bus of FLASH ROM
O
0
106
DVSS7
GND
-
0
107
A17
Address bus of FLASH ROM
O
3.3
108
A18
Address bus of FLASH ROM
O
0
109
A19
Address bus of FLASH ROM
O
0
110
A20
Address bus of FLASH ROM
O
0
111
CVSS9
GND
-
0
112
DVDD5
I/O system (3.3V) power supply
-
3.3
113
D6
Data bus of FLASH ROM
I/O
0
114
D7
I/O
0
115
D8
I/O
0
116
D9
I/O
0
117
D10
I/O
0
6
CQ-C3401W
Pin
No.
Port
Descriptions
I/O
(V)
118
D11
Data bus of FLASH ROM
I/O
0
119
D12
I/O
0
120
STAT
Status signal input
I
0.4
121
D13
Data path of FLASH ROM
I/O
0
122
D14
I/O
0
123
D15
I/O
0
124
-
-
-
-
125
CVDD6
CORE CPU system (1.6V) power
supply
supply
-
1.6
126
CVSS10
GND
-
0
127
-
-
-
-
128
DVSS8
I/O system (3.3V) power supply
-
0
129
-
-
-
-
130
DVDD6
I/O system (3.3V) power supply
-
3.3
131
A0
Address bus of FLASH ROM
O
0
132
A1
O
0
133
A2
O
3.3
134
A3
O
3.3
135
/RST
Reset signal output (To Servo DSP)
O
3.3
136
A4
Address bus of FLASH ROM
O
3.3
137
A5
O
0
138
A6
O
3.3
139
A7
O
3.3
140
A8
O
0
141
A9
O
3.3
142
CVDD7
CORE CPU system (1.6V) power
supply
supply
-
1.6
143
-
-
-
-
144
DVSS9
GND
-
0
7
CQ-C3401W
10 PACKAGE AND IC BLOCK DIAGRAM
10.1. Main Block
PA051 : YESAP403
IC201 : C1BB00000543
IC271 : YESAM274
8
CQ-C3401W
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