LG 60LN54XX / 60LN5400 / 60LN5420 / 60LN542Y (CHASSIS:LB31F / LB36B) Service Manual ▷ View online
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
+3.5V_ST
/FLASH_WP
C5501
0.1uF
IC1300-*2
W25Q80BVSSIG
SFLASH_OS_WINBOND
3
%WP[IO2]
2
DO[IO1]
4
GND
1
CS
5
DI[IO0]
6
CLK
7
HOLD[IO3]
8
VCC
R5504
33
33
SPI_SCK
R5503
4.7K
OPT
SPI_SDO
SPI_SDI
R5501
10K
10K
OPT
+3.5V_ST
/SPI_CS
R5502
0
0
+3.5V_ST
IC1300-*3
MX25L8006EM2I-12G
SFLASH_OS_MACRONIX
3
WP#
2
SO/SIO1
4
GND
1
CS#
5
SI/SIO0
6
SCLK
7
HOLD#
8
VCC
IC1300-*1
MX25L6406EM2I-12G
SFLASH_NON_OS_MX
3
WP
2
SO/SIO1
4
GND
1
CS
5
SI/SIO0
6
SCLK
7
HOLD
8
VCC
IC1300
W25Q64FVSSIG
SFLASH_NON_OS_WINBOND
3
WP[IO2]
2
DO[IO1]
4
GND
1
CS
5
DI[IO0]
6
CLK
7
%HOLD[IO3]
8
VCC
S_FLASH_NON_OS
2012.06.21
55
NC4_S7LRM
Serial Flash for SPI boot_NON_OS
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
FRC_A[9]
FRC_DQU[6]
FRC_A[6]
FRC_DQU[3]
FRC_DQL[7]
FRC_DQL[1]
FRC_A[0]
FRC_DQU[7]
FRC_A[2]
FRC_A[3]
FRC_DQL[0]
FRC_DQL[5]
FRC_DQU[2]
FRC_DQU[4]
FRC_A[5]
FRC_DQU[5]
FRC_DQL[6]
FRC_A[8]
FRC_DQL[4]
FRC_A[4]
FRC_DQL[3]
FRC_A[12]
FRC_DQL[2]
FRC_A[11]
FRC_DQU[0]
FRC_A[10]
FRC_A[13]
FRC_DQU[1]
FRC_A[7]
FRC_A[1]
GPIO[8]
C6117
0.1uF
0.1uF
URSA_MODEL_OPT_3
TXB1N
TXA2P
TXC0N
+3.3V_FRC
SDA2_+3.3V_URSA
FRC_VDDC10
R6113
10K
R6149
33
R6128
100
L6105
BLM18SG121TN1D
TXA0N
SCL2_+3.3V_DB
SDA2_+3.3V_URSA
TXD2P
TXB3P
R6126
33
R6141
1M
R6104
10K
OPT
FRC_DQL[0-7]
FRC_DDR3_RESETB
+3.3V_FRC
GPIO[1]
IC6102
W25X20BVSNIG
URSA5_FLASH_WINBOND_2M
3
WP
2
DO
4
GND
1
CS
5
DIO
6
CLK
7
HOLD
8
VCC
L6101
BLM18SG121TN1D
FRC_CASB
TXBCLKP
TP6101
FRC_A[0-13]
FRC_AVDD_LVDS33
+1.5V_FRC_DDR
R6118
10K
OPT
SPI_DO
TXB2N
SDA2_+3.3V_DB
R6137
100
FRC_AVDD_PLL
FRC_AVDD_LVDS33
SPI_DI
+1.5V_FRC_DDR
+1.5V_FRC_DDR
TP6104
R6146
4.7K
C6131
0.1uF
0.1uF
SDA2_+3.3V_DB
TXDCLKP
FRC_BA0
+1.26V_FRC
C6112
22uF
10V
22uF
10V
AFRC_VDD33
C6106
0.1uF
0.1uF
R6131
100
R6135
100
R6150
33
C6109
22uF
10V
22uF
10V
TXC3P
TXC1N
C6113
0.1uF
0.1uF
C6125
0.22uF
6.3V
0.22uF
6.3V
PWM0_CONFIG
TXD2N
+3.3V_FRC
R6112
10K
OPT
IC6101
LGE7303C
DDR3_A0/DDR2_NC
P14
DDR3_A1/DDR2_A8
G15
DDR3_A2/DDR2_NC
N14
DDR3_A3/DDR2_A10
L15
DDR3_A4/DDR2_A2
H15
DDR3_A5/DDR2_A3
L14
DDR3_A6/DDR2_A4
G14
DDR3_A7/DDR2_A5
N12
DDR3_A8/DDR2_A6
G13
DDR3_A9/DDR2_A9
N13
DDR3_A10/DDR2_RASZ
H14
DDR3_A11/DDR2_A11
F15
DDR3_A12/DDR2_A0
H13
DDR3_A13/DDR2_A12
P13
DDR3_BA0/DDR2_BA2
M12
DDR3_BA1/DDR2_CASZ
H12
DDR3_BA2/DDR2_A1
L13
DDR3_MCLK/DDR2_MCLK
F16
DDR3_MCLKZ/DDR2_MCLKZ
F17
DDR3_CKE/DDR2_ODT
J13
DDR3_ODT/DDR2_CKE
K12
DDR3_RASZDDR2_WEZ
L12
DDR3_CASZ/DDR2_BA1
K13
DDR3_WEZ/DDR2_BA0
K14
DDR3_RESET/DDR2_A7
M14
DDR3_DQSL/DDR2_DQSL
N16
DDR3_DQSU/DDR2_DQSU
M17
DDR3_DQSBL/DDR2_DQSBL
M16
DDR3_DQSBU/DDR2_DQSBU
M15
DDR3_DQML/DDR2_DQU5
J15
DDR3_DQMU/DDR2_DQU4
R16
DDR3_DQL0/DDR2_DQU3
R17
DDR3_DQL1/DDR2_DQL0
H17
DDR3_DQL2/DDR2_DQL6
R15
DDR3_DQL3/DDR2_DQL7
J17
DDR3_DQL4/DDR2_DQL3
T17
DDR3_DQL5/DDR2_DQL2
H16
DDR3_DQL6/DDR2_DQL1
T15
DDR3_DQL7/DDR2_DQL5
G16
DDR3_DQU0/DDR2_DQU7
K15
DDR3_DQU1/DDR2_DQML
N15
DDR3_DQU2/DDR2_DQU2
K17
DDR3_DQU3/DDR2_DQU6
P17
DDR3_DQU4/DDR2_NC
L17
DDR3_DQU5/DDR2_DQU1
P16
DDR3_DQU6/DDR2_DQU0
K16
DDR3_DQU7/DDR2_DQMU
P15
I2CM_SCL
D14
I2CM_SDA
D15
I2CS_SCL
P1
I2CS_SDA
P2
DDR3_NC/DDR2_A13
F14
DDR3_NC/DDR2_DQL4
T16
VSS_1
D6
VSS_2
D7
VSS_3
D8
VSS_4
D9
VSS_5
E6
VSS_6
E7
VSS_7
E8
VSS_8
E9
VSS_9
E10
VSS_10
E16
VSS_11
F3
VSS_12
F6
VSS_13
F7
VSS_14
F8
VSS_15
F9
VSS_16
G1
VSS_17
G2
VSS_18
G4
VSS_19
G5
VSS_20
G6
VSS_21
G7
VSS_22
G8
VSS_23
G9
VSS_24
G17
VSS_25
H1
VSS_26
H2
VSS_27
H4
VSS_28
H5
VSS_29
H6
VSS_30
H7
VSS_31
H8
VSS_32
H9
VSS_33
H10
VSS_34
H11
VSS_35
J4
VSS_36
J5
VSS_37
J6
VSS_38
J7
VSS_39
J8
VSS_40
J9
VSS_41
J10
VSS_42
J11
VSS_43
J12
VSS_44
J14
VSS_45
J16
VSS_46
K4
VSS_47
K5
VSS_48
K6
VSS_49
K7
VSS_50
K8
VSS_51
K11
VSS_52
L6
VSS_53
L7
VSS_54
L8
VSS_55
L11
VSS_56
L16
VSS_57
M6
VSS_58
M7
VSS_59
M8
VSS_60
M11
VSS_61
M13
VSS_62
N6
VSS_63
N7
VSS_64
N8
VSS_65
N17
VSS_66
P3
VSS_67
P4
VSS_68
P5
VSS_69
P6
VSS_70
P7
VSS_71
P12
VSS_72
U16
NC
L9
HW_RESET
J3
TESTPIN_1
D1
TESTPIN_2
D2
TESTPIN_3
D3
TESTPIN_4
E1
TESTPIN_5
E2
TESTPIN_6
E3
TESTPIN_7
F1
TESTPIN_8
F2
M0_SCLK
C17
M0_MOSI
D16
M1_SCLK
D17
M1_MOSI
E15
M2_SCLK
E14
M2_MOSI
E13
M3_SCLK
E12
M3_MOSI
F13
SPI_CK
T9
SPI_CZ
U10
SPI_DI
U9
SPI_DO
T10
TXA0P/GCLK6/BLUE[7]
C8
TXA0N/GCLK5/BLUE[6]
C9
TXA1P/OPT_N/LK3/BLUE[9]
B8
TXA1N/FLK/BLUE[8]
A8
TXA2P/GREEN[1]
A7
TXA2N/OPT_P/LK2/GREEN[0]
B7
TXACLKP/RLV0N/GREEN[3]
C6
TXACLKN/RLV0P/GREEN[2]
C7
TXA3P/RLV1N/GREEN[5]
B6
TXA3N/RLV1P/GREEN[4]
A6
TXA4P/RLV2N/GREEN[7]
A5
TXA4N/RLV2P/GREEN[6]
B5
TXB0P/RLV3N/GREEN[9]
C4
TXB0N/RLV3P/GREEN[8]
C5
TXB1P/RLVCLKN/RED[1]
B4
TXB1N/RLVCLKP/RED[0]
A4
TXB2P/RLV4P/RED[3]/EPI_A3P
A3
TXB2N/RLV4N/RED[2]/EPI_A3N
B3
TXBCLKP/RLV5N/RED[5]/EPI_A2P
C2
TXBCLKN/RLV5P/RED[4]/EPI_A2N
C3
TXB3P/RLV6N/RED[7]/EPI_A1P
B2
TXB3N/RLV6P/RED[6]/EPI_A1N/
A2
TXB4P/RLV7N/RED[9]/EPI_A0P
C1
TXB4N/RLV7P/RED[8]/EPI_A0N
B1
TXC0P/SOE
C16
TXC0N/POL
B17
TXC1P/GSP_R
B16
TXC1N/GSP/VST
A16
TXC2P/GOE/GCLK1
A15
TXC2N/GSC/GCLK3
B15
TXCCLKP/LLV0N
C14
TXCCLKN/LLV0P
C15
TXC3P/LLV1N
B14
TXC3N/LLV1P
A14
TXC4P/LLV2N
A13
TXC4N/LLV2P
B13
TXD0P/LLV3N
C12
TXD0N/LLV3P
C13
TXD1P/LLVCLKN
B12
TXD1N/LLVCLKP
A12
TXD2P/LLV4N/EPI_B3P
A11
TXD2N/LLV4P/EPI_B3N
B11
TXDCLKP/LLV5N/BLUE[1]/EPI_B2P
C10
TXDCLKN/LLV5P/BLUE[0]/EPI_B2N
C11
TXD3P/LLV6N/BLUE[3]
B10
TXD3N/LLV6P/BLUE[2]/EPI_B1N
A10
TXD4P/LLV7N/BLUE[5]/EPI_B0P
A9
TXD4N/LLV7P/BLUE[4]/EPI_B0N
B9
MOD_GPIO0/VDD_ODD/HSYNC
D10
MOD_GPIO1/VDD_EVEN/VSYNC
D11
MOD_GPIO2/PWM13/GCLK4/LCK
D12
MOD_GPIO3/PWM14/GCLK2/LDE
D13
PWM0/SCAN_BLK1
U12
PWM1/SCAN_BLK2
T12
LPLL_FBCLK
G3
LPLL_OUTCLK
E17
LPLL_REFIN
H3
AVDD_1
F4
AVDD_2
F5
AVDD_DDR_C_1
F10
AVDD_DDR_C_2
G10
AVDD_DDR_D_1
F11
AVDD_DDR_D_2
F12
AVDD_DDR_D_3
G11
AVDD_DDR_D_4
G12
AVDD_LVDS3.3V_1
D4
AVDD_LVDS3.3V_2
D5
AVDD_LVDS3.3V_3
E4
AVDD_LVDS3.3V_4
E5
AVDD_MPLL3.3V
M5
AVDD_LPLL3.3V
L4
AVDD_PLL3.3V
L5
AVDDL_MOD1.26V
K10
DVDD_DDR_1.26V
L10
DVDD_HF1.26V
K9
VD33_1
M4
VD33_2
N4
VD33_3
N5
VDDC_1.26V_1
M9
VDDC_1.26V_2
M10
VDDC_1.26V_3
N9
VDDC_1.26V_4
N10
VDDC_1.26V_5
N11
VDDC_1.26V_6
P10
VDDC_1.26V_7
P11
RXBCLKP
R2
RXBCLKN
R3
RXB0P
R4
RXB0N
R5
RXB1P
T4
RXB1N
U4
RXB2P
U3
RXB2N
T3
RXB3P
T2
RXB3N
U2
RXB4P
T1
RXB4N
R1
RXACLKP
R6
RXACLKN
R7
RXA0P
R8
RXA0N
R9
RXA1P
T8
RXA1N
U8
RXA2P
U7
RXA2N
T7
RXA3P
T6
RXA3N
U6
RXA4P
U5
RXA4N
T5
XTALO
J1
XTALI
J2
GPIO0/(UART_RX/S_PIF_DA0)
R13
GPIO1
P9
GPIO2/(S_PIF_CLK)
T13
GPIO3/(LTD_DA1)
U15
GPIO4/(LTD_DE)
R14
GPIO5/(LTD_CLK)
K2
GPIO6/(LTD_DA0)
K1
GPIO7(3D_FLAG)
T14
GPIO8
P8
GPIO9/(UART_TX/S_PIF_DA1)
U14
GPIO10/(S_PIF_FC)
U13
GPIO11/(S_PIF_CS)
R12
VSYNC_LIKE
E11
M_S_PIF_CLK
N2
M_S_PIF_CS
M1
M_S_PIF_DA0
N1
M_S_PIF_DA1
N3
M_S_PIF_FC
M3
S_M_PIF_CLK
L1
S_M_PIF_CS
M2
S_M_PIF_DA0
L2
S_M_PIF_DA1
K3
S_M_PIF_FC
L3
SOFT_RST_L
R10
SOFT_RST_R
T11
OP_SYNC_L
R11
OP_SYNC_R
U11
C6103
0.1uF
0.1uF
FRC_DMU
R6117
10K
OPT
SPI_SCLK
TXD3P
C6104
0.1uF
0.1uF
+3.3V_FRC
TXC4N
TXC2P
C6110
0.1uF
0.1uF
C6135
0.1uF
R6148
10K
+3.3V_FRC
R6133
10K
10K
TXB1P
R6110
10K
OPT
R6134
100
FRC_VDD33
FRC_DML
URSA_MODEL_OPT_3
SPI_CS
FRC_AVDD_LVDS33
AFRC_VDD33
PWM0_CONFIG
L6106
BLM18SG121TN1D
C6132
0.1uF
0.1uF
R6115
10K
OPT
C6126
0.1uF
0.1uF
C6120
0.22uF
6.3V
0.22uF
6.3V
TXA4P
FRC_DQSLB
FRC_DQSU
+3.3V_FRC
TXC4P
C6122
0.1uF
0.1uF
FRC_VDD33
FRC_DQSUB
SCL2_+3.3V_URSA
R6106
10K
OPT
FRC_VDD33
R6108
10K
OPT
PWM1_CONFIG
FRC_BA2
FRC_AVDD_PLL
TXA2N
TXACLKN
R6139
100
TXC2N
FRC_WEB
FRC_RESET
TP6102
FRC_BA1
FRC_VDDC10
R6143
33
R6119
0
0
URSA5_MP
TXDCLKN
R6151
3.3K
C6124
0.1uF
0.1uF
FRC_MCKB
R6147
33
TP6105
R6120
0
OPT
OPT
SCL2_+3.3V_URSA
FRC_DQSL
R6129
100
PWM1_CONFIG
C6101
0.1uF
0.1uF
TXB0N
TXD0N
R6111
10K
R6127
100
P6101
12505WS-04A00
URSA5_DEBUG
1
2
3
4
5
R6122
0
OPT
OPT
R6107
10K
FRC_VDDC10
R6136
100
URSA_MODEL_OPT_2
C6118
0.1uF
0.1uF
C6114
22uF
10V
22uF
10V
+3.3V_FRC
FRC_ODT
SPI_DO
C6107
0.1uF
0.1uF
R6138
100
TXB3N
AFRC_VDD33
TXA0P
TXCCLKP
DVDD_DDR_1V
URSA_MODEL_OPT_0
R6130
100
TXB0P
FRC_CKE
TXD1P
TXB4N
TXD4N
R6114
10K
OPT
+3.3V_FRC
FRC_AVDD_PLL
C6119
0.1uF
0.1uF
TXC3N
R6103
10K
R6125
33
FRC_RASB
R
6
1
4
2
0
OPT
TXC0P
TXA4N
TXA3N
C6130
0.22uF
6.3V
0.22uF
6.3V
TXD0P
R6145
33
C6123
0.1uF
0.1uF
C6128
0.1uF
0.1uF
TXD4P
SPI_DI
C6129
0.1uF
0.1uF
TXC1P
R6140
33
C6102
0.1uF
0.1uF
TXBCLKN
URSA_SCL
TXD1N
L6103
BLM18SG121TN1D
R6144
33
DVDD_DDR_1V
R6116
10K
SPI_SCLK
URSA_MODEL_OPT_1
C6105
0.1uF
0.1uF
TXB2P
TP6103
TXACLKP
SCL2_+3.3V_DB
C6115
10uF
6.3V
10uF
6.3V
R6101
22
URSA5_DEBUG
R6109
10K
OPT
FRC_MCK
R6132
100
+1.26V_FRC
URSA_MODEL_OPT_0
URSA_MODEL_OPT_2
TXCCLKN
C6133
0.1uF
0.1uF
TP6106
URSA_SDA
TXB4P
TXA1P
C6121
0.1uF
0.1uF
L6102
BLM18SG121TN1D
GPIO[1]
L6104
BLM18SG121TN1D
TXA3P
C6127
0.1uF
0.1uF
GPIO[8]
R6102
22
URSA5_DEBUG
TXA1N
R6105
10K
OPT
SPI_CS
SW6101
JS2235S
URSA5_DEBUG
3
2
1
4
5
6
FRC_DQU[0-7]
TXD3N
R6121
0
URSA5_MP
URSA_MODEL_OPT_1
RXA0+
RXA4-
RXA4+
RXA0-
RXA3-
RXA1+
RXA3+
RXA1-
RXACK+
RXACK-
RXA2+
RXA2-
RXB0+
RXB4-
RXB4+
RXB0-
RXB1+
RXB1-
RXB2-
RXBCK+
RXB2+
RXBCK-
RXB3+
RXB3-
C6111
10uF
10uF
C6108
10uF
10uF
C6116
10uF
10uF
R6123
2.2K
1/16W
5%
R6124
2.2K
1/16W
5%
C6134
1uF
10V
1uF
10V
X6101
24MHz
4
GND_2
1
X-TAL_1
2
GND_1
3
X-TAL_2
C6136
10pF
C6137
10pF
+3.3V_FRC
URSA5
61
2012. 10. 10
NC4_S7LRM
(VDDP)
D13
MODEL OPTION
URSA_MODEL_OPT_3
CHIP_CONF : {GPIO8, PWM1, PWM0}
CHIP_CONF = 3’d5 : boot from interal SRAM
CHIP_CONF = 3’d6 : boot from EEPROM
CHIP_CONF = 3’d7 : boot from SPI Flash
CHIP_CONF = 3’d5 : boot from interal SRAM
CHIP_CONF = 3’d6 : boot from EEPROM
CHIP_CONF = 3’d7 : boot from SPI Flash
L/DIM_10BLOCK
URSA_MODEL_OPT_0
RESERVED
RESERVED
LVDS_S7M_PLUS
GPIO1 : HI => B8/94, LOW => B4/98
URSA5 CONFIGURATION
URSA5 H/W OPTION
D10
URSA_MODEL_OPT_1
LVDS_EXT_URSA5
PLACE TERMINATION RESISTORS CLOSE TO URSA5
[SPI FLASH(2Mbit)]
PIN NAME
LOW
PIN NO.
URSA_MODEL_OPT_2
D12
L/DIM_16BLOCK
Debugging for URSA5
Place Close to Bead
D11
RESERVED
HIGH
RESERVED
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
FRC_DQL[1]
FRC_A[9]
FRC_DQU[2]
FRC_DQL[4]
FRC_A[5]
FRC_A[4]
FRC_DQL[6]
FRC_DQL[3]
FRC_DQU[5]
FRC_DQU[6]
FRC_A[10]
FRC_A[3]
FRC_A[6]
FRC_A[11]
FRC_DQL[0]
FRC_DQL[7]
FRC_DQU[0]
FRC_A[8]
FRC_A[7]
FRC_DQU[3]
FRC_DQU[4]
FRC_A[1]
FRC_A[13]
FRC_DQU[1]
FRC_DQU[7]
FRC_A[0]
FRC_A[2]
FRC_DQL[5]
FRC_A[12]
FRC_DQL[2]
FRC_DQSUB
FRC_CKE
C6204
22uF
10V
22uF
10V
FRC_CASB
C6205
0.1uF
R6202
1K
1%
1%
R6203
1K
1%
1%
FRC_MCK
+1.5V_FRC_DDR
FRC_DQSL
C6208
0.1uF
C6213
0.1uF
C6203
0.1uF
16V
0.1uF
16V
C6212
0.1uF
C6206
0.1uF
FRC_DQL[0-7]
R6204
1K
1%
1%
C6202
0.1uF
FRC_DQSU
MVREFCA
FRC_DMU
FRC_BA1
MVREFDQ
+1.5V_FRC_DDR
FRC_DDR3_RESETB
R6201
1K
1%
+1.5V_FRC_DDR
FRC_DQU[0-7]
R6206
150
OPT
FRC_DQSLB
MVREFDQ
FRC_MCK
FRC_MCKB
FRC_DML
+1.5V_FRC_DDR
FRC_BA2
C6210
0.1uF
MVREFCA
R6205
240
1%
C6215
0.01uF
50V
0.01uF
50V
FRC_BA0
C6201
0.1uF
FRC_RASB
+1.5V_FRC_DDR
FRC_MCKB
+1.5V_FRC_DDR
H5TQ1G63EFR-PBC
IC6201
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
NC_7
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
C6214
0.1uF
C6211
0.1uF
FRC_A[0-13]
R6207
510
R6209
56
56
FRC_ODT
R6208
56
56
C6207
0.1uF
FRC_WEB
C6209
0.1uF
URSA5_DDR3
62
NC4_S7LRM
2012. 10.10
Place Close to DDR Pin
Place Close to DDR Pin
DDR3 1.5V De-Cap Place near Memory
Close to DDR Pin
THERMAL
THERMAL
THERMAL
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
R6312
10K
10K
C6309
3300pF
50V
3300pF
50V
C6317
10uF
10V
+3.3V_FRC
C6305
1uF
10V
1uF
10V
R6315
1K
1%
IC6302
TPS54327DDAR
3
VREG5
2
VFB
4
SS
1
EN
5
GND
6
SW
7
VBST
8
VIN
9
[EP]GND
+3.3V_FRC
R6309
10K
IC6301
TPS54327DDAR
3
VREG5
2
VFB
4
SS
1
EN
5
GND
6
SW
7
VBST
8
VIN
9
[EP]GND
C6312
0.1uF
16V
16V
+12V
R6310
330K
OPT
OPT
+12V
R
6
3
0
8
1
2
K
1
%
+1.26V_FRC
C6301
10uF
16V
10uF
16V
C6302
10uF
16V
10uF
16V
C6320
560pF
50V
R6304
220
1%
C6314
22uF
10V
22uF
10V
R6301
6.8K
6.8K
1%
C6313
22uF
10V
22uF
10V
L6301
BLM18PG121SN1D
C6308
1uF
10V
1uF
10V
C6310
3300pF
50V
3300pF
50V
R6313
4.3K
1%
R6311
10K
1/16W
5%
R6305
10K
OPT
C6315
22uF
10V
22uF
10V
OPT
0.1uF
C6318
16V
C6321
10uF
16V
C6322
10uF
16V
R6314
3.9K
1%
R6307
10K
1%
C6311
0.1uF
16V
16V
+3.3V_FRC
+12V
+1.5V_FRC_DDR
C6307
1uF
25V
1uF
25V
R6302
33K
33K
1%
1uF
C6319
10V
R6303
1K
1K
1%
C6303
27pF
50V
POWER_ON/OFF_1
C6316
22uF
10V
22uF
10V
C6304
100pF
50V
L6302
BLM18PG121SN1D
C6306
1uF
10V
1uF
10V
IC6303
AP7173-SPG-13 HF(DIODES)
EAN41406705
3
VCC
2
PG
4
EN
1
IN
5
GND
6
SS
7
FB
8
OUT
9
[EP]
D6301
5V
OPT
D6302
5V
OPT
D6303
5V
OPT
L6304
3.6uH
3.6uH
LPB8040T-3R6N
L6303
3.6uH
3.6uH
LPB8040T-3R6N
NC4_S7LRM
2012. 10. 10
URSA5_POWER
63
Vout=0.765*(1+R1/R2)
+1.5V of DDR&URSA5 uses same power line
R2
+3.3V_FRC
Vout=0.765*(1+R1/R2)
Vout=0.6*(1+R1/R2)
R2
3A
R1
TYPICAL 350mA
+1.5V_FRC
CORE +1.26V_FRC
R1
3A
R2
TYPICAL 980mA
Switching freq: 700K
Switching freq: 700K
R1
TYPICAL 300mA
Click on the first or last page to see other 60LN54XX / 60LN5400 / 60LN5420 / 60LN542Y (CHASSIS:LB31F / LB36B) service manuals if exist.