LG 55LEX8-ZA (CHASSIS:LD03S) Service Manual ▷ View online
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
DDR1_DQS1
004:H3
DDR0_CLKb
0 0 4 : C 7 ; 0 0 4 : C 4
DDR0_VREF0
DDR1_CLK
0 0 4 : A 7 ; 0 0 4 : F 4
DDR01_CASb
0.1uF
C477
470pF
C479
0.1uF
C455
DDR01_CASb
0.047uF
C441
0 . 1 u F
C466
DDR1_A[4-6]
100
1%
R407
0 . 1 u F
C491
0.047uF
C482
DDR01_BA2
DDR01_BA0
75
R409
0.1uF
C406
DDR01_WEb
D1.8V
DDR0_DQS1b
0 0 4 : E 3
DDR01_A[0-3,7-13]
DDR01_BA0
75
AR408
DDR01_BA1
0.047uF
C478
470pF
C409
D1.8V
DDR01_BA0
DDR1_DQ[0-7]
DDR0_DM0
0 0 4 : E 6
DDR01_WEb
DDR01_CKE
0 . 1 u F
C492
DDR01_BA2
470pF
C464
DDR0_DQS0
004:A4
DDR01_CASb
DDR1_DQS0
004:A4
75
AR403
DDR01_A[7-13]
DDR0_DQ[0-7] 004:B6
DDR01_BA1
D1.8V
DDR01_CKE
DDR01_A[0-3,7-13]
0.1uF
C442
DDR01_CASb
DDR01_BA1
DDR01_A[0-3]
DDR01_WEb
DDR01_BA1
DDR01_WEb
DDR01_WEb
DDR01_CKE
DDR1_DQS0
004:H6
D1.8V
DDR01_BA2
DDR01_BA0
470pF
C453
DDR01_RASb
0.047uF
C445
DDR1_DQ[0-7]
004:B5
DDR1_CLK
0 . 1 u F
C403
DDR01_BA2
470pF
C408
OPT
0.047uF
C465
75
R410
DDR01_ODT
0.1uF
C415
DDR01_WEb
75
AR404
470pF
C463
0.047uF
C471
DDR01_BA0
DDR01_BA0
DDR0_VREF0
0.047uF
C460
DDR0_DQS1
0 0 4 : E 3
0 . 1 u F
C493
DDR01_WEb
0.1uF
C459
470pF
C402
OPT
75
R408
75
AR409
DDR01_BA1
DDR0_DM1
0 0 4 : E 3
DDR1_CLK
0 0 4 : F 7 ; 0 0 4 : F 4
DDR0_A[4-6]
DDR01_BA0
DDR01_CASb
DDR0_A[4-6]
75
AR407
0.047uF
C456
DDR01_BA2
DDR0_CLK
0 0 4 : A 7 ; 0 0 4 : C 7
DDR1_DQ[8-15]
DDR_VTT
DDR01_BA1
DDR1_DQS0b
004:A3
DDR01_CKE
0 0 4 : A 7 ; 0 0 4 : C 7 ; 0 0 4 : F 7 ; 0 0 4 : F 4
DDR01_CKE
DDR0_CLKb
0 0 4 : A 7 ; 0 0 4 : C 4
470pF
C440
75
R404
DDR01_RASb
0.1uF
C481
DDR01_ODT
470pF
C470
DDR0_DQ[0-7]
470pF
C400
DDR0_CLKb
0 0 4 : A 7 ; 0 0 4 : C 7
DDR1_DQS1b
004:A3
75
AR406
DDR01_ODT
D1.8V
0 . 1 u F
C484
DDR0_DM0
004:A4
DDR1_A[4-6]
0 0 4 : B 6 ; 0 0 4 : F 6 ; 0 0 4 : I 7
470pF
C461
DDR01_ODT
DDR0_DQ[8-15]
DDR1_VREF0
DDR01_BA1
DDR01_A[0-3,7-13]
0 . 1 u F
C450
DDR01_ODT
0 0 4 : A 7 ; 0 0 4 : C 5 ; 0 0 4 : C 2 ; 0 0 4 : F 2 ; 0 0 4 : I 4 ; 0 0 4 : I 6
DDR01_RASb
DDR1_CLKb
0 0 4 : F 7 ; 0 0 4 : F 4
DDR01_RASb
470pF
C462
D1.8V
DDR01_RASb
0 . 1 u F
C467
0.1uF
C446
DDR01_A[0-3,7-13]
DDR1_A[4-6]
0 0 4 : B 6 ; 0 0 4 : F 3 ; 0 0 4 : I 7
75
AR401
DDR01_A[0-3,7-13]
DDR1_DM1
004:H3
DDR0_DQS1b
004:A4
DDR1_DQS1b
004:H3
DDR1_DQS1
004:A3
DDR01_ODT
DDR0_DM1
004:A4
470pF
C495
DDR01_BA2
D1.8V
DDR0_CLK
0 0 4 : A 7 ; 0 0 4 : C 4
DDR0_DQS0
0 0 4 : E 6
0.1uF
C468
0 . 1 u F
C404
DDR01_RASb
470pF
C452
DDR1_CLKb
0 0 4 : A 7 ; 0 0 4 : F 4
0 . 1 u F
C449
DDR0_A[4-6]
DDR0_DQ[8-15]
22uF
C475
22uF
C451
100
1%
R406
DDR0_DQS0b
004:A4
DDR_VTT
0 . 1 u F
C483
470pF
C457
DDR01_RASb
DDR1_CLKb
240
1%
R412
470pF
C444
0 . 1 u F
C494
DDR1_DM0
004:H6
DDR01_CASb
A1.2V
DDR0_CLK
0 0 4 : C 7 ; 0 0 4 : C 4
75
AR405
0.1uF
C472
DDR1_DM1
004:A4
75
AR400
DDR1_DQS0b
004:H6
75
AR402
DDR1_DM0
004:A4
DDR0_A[4-6]
DDR1_A[4-6]
DDR1_DQ[8-15]
004:B5
DDR0_DQS0b
0 0 4 : E 6
0
OPT
R411
DDR01_ODT
DDR1_VREF0
DDR01_BA2
DDR0_DQS1
004:A4
10uF
C473
10uF
C476
10uF
C454
10uF
C448
10uF
C469
10uF
C443
10uF
C480
10uF
C458
1uF
C401
1uF
C410
1uF
C407
1uF
C405
10uF
C474
10uF
C447
0 . 1 u F
C496
0 . 1 u F
C497
0 . 1 u F
C498
0 . 1 u F
C490
0 . 1 u F
C487
0 . 1 u F
C486
0 . 1 u F
C488
0 . 1 u F
C485
0 . 1 u F
C489
0 . 1 u F
C499
0 . 1 u F
C421
DDR01_CKE
DDR01_CKE
220
R417
0 . 1 u F
16V
16V
C412
10uF
10V
C417
10uF
10V
10V
C419
DDR1_VREF0
10uF
10V
10V
C416
1uF
10V
10V
C418
0.1uF
1
6
V
C414
DDR_VTT
10K
R418
1uF
10V
C422
D3.3V
0 . 1 u F
16V
16V
C413
D1.8V
10uF
10V
C423
0 . 1 u F
16V
16V
C411
BD35331F-E2
IC404
3
VTTS
2
EN
4
VREF
1
GND
5
VDDQ
6
VCC
7
VTT_IN
8
VTT
0 . 1 u F
16V
16V
C420
DDR0_VREF0
NT5TU128M8DE_BD
IC403
CK
E8
CK
F8
CKE
F2
RAS
F7
CAS
G7
WE
F3
CS
G8
BA0
G2
BA1
G3
NC_1/BA2
G1
A0
H8
A1
H3
A2
H7
A3
J 2
A4
J 8
A5
J 3
A6
J 7
A7
K2
A8
K8
A9
K3
A10/AP
H2
A11
K7
A12
L2
A13
L8
NC_2/A14
L3
NC_3/A15
L7
ODT
F9
DQ0
C8
DQ1
C2
DQ2
D7
DQ3
D3
DQ4
D1
DQ5
D9
DQ6
B1
DQ7
B9
DQS
B7
DQS
A8
DM/RDQS
B3
NU/RDQS
A2
VDDQ_1
A9
VDDQ_2
C1
VDDQ_3
C3
VDDQ_4
C7
VDDQ_5
C9
VDD_1
A1
VDD_2
L1
VDD_3
E9
VDD_4
H9
VSSQ_1
A7
VSSQ_2
B2
VSSQ_3
B8
VSSQ_4
D2
VSSQ_5
D8
VSS_1
A3
VSS_2
E3
VSS_3
J 1
VSS_4
K9
VREF
E2
VDDL
E1
VSSDL
E7
NT5TU128M8DE_BD
IC402
CK
E8
CK
F8
CKE
F2
RAS
F7
CAS
G7
WE
F3
CS
G8
BA0
G2
BA1
G3
NC_1/BA2
G1
A0
H8
A1
H3
A2
H7
A3
J 2
A4
J 8
A5
J 3
A6
J 7
A7
K2
A8
K8
A9
K3
A10/AP
H2
A11
K7
A12
L2
A13
L8
NC_2/A14
L3
NC_3/A15
L7
ODT
F9
DQ0
C8
DQ1
C2
DQ2
D7
DQ3
D3
DQ4
D1
DQ5
D9
DQ6
B1
DQ7
B9
DQS
B7
DQS
A8
DM/RDQS
B3
NU/RDQS
A2
VDDQ_1
A9
VDDQ_2
C1
VDDQ_3
C3
VDDQ_4
C7
VDDQ_5
C9
VDD_1
A1
VDD_2
L1
VDD_3
E9
VDD_4
H9
VSSQ_1
A7
VSSQ_2
B2
VSSQ_3
B8
VSSQ_4
D2
VSSQ_5
D8
VSS_1
A3
VSS_2
E3
VSS_3
J 1
VSS_4
K9
VREF
E2
VDDL
E1
VSSDL
E7
NT5TU128M8DE_BD
IC401
CK
E8
CK
F8
CKE
F2
RAS
F7
CAS
G7
WE
F3
CS
G8
BA0
G2
BA1
G3
NC_1/BA2
G1
A0
H8
A1
H3
A2
H7
A3
J 2
A4
J 8
A5
J 3
A6
J 7
A7
K2
A8
K8
A9
K3
A10/AP
H2
A11
K7
A12
L2
A13
L8
NC_2/A14
L3
NC_3/A15
L7
ODT
F9
DQ0
C8
DQ1
C2
DQ2
D7
DQ3
D3
DQ4
D1
DQ5
D9
DQ6
B1
DQ7
B9
DQS
B7
DQS
A8
DM/RDQS
B3
NU/RDQS
A2
VDDQ_1
A9
VDDQ_2
C1
VDDQ_3
C3
VDDQ_4
C7
VDDQ_5
C9
VDD_1
A1
VDD_2
L1
VDD_3
E9
VDD_4
H9
VSSQ_1
A7
VSSQ_2
B2
VSSQ_3
B8
VSSQ_4
D2
VSSQ_5
D8
VSS_1
A3
VSS_2
E3
VSS_3
J 1
VSS_4
K9
VREF
E2
VDDL
E1
VSSDL
E7
NT5TU128M8DE_BD
IC400
CK
E8
CK
F8
CKE
F2
RAS
F7
CAS
G7
WE
F3
CS
G8
BA0
G2
BA1
G3
NC_1/BA2
G1
A0
H8
A1
H3
A2
H7
A3
J 2
A4
J 8
A5
J 3
A6
J 7
A7
K2
A8
K8
A9
K3
A10/AP
H2
A11
K7
A12
L2
A13
L8
NC_2/A14
L3
NC_3/A15
L7
ODT
F9
DQ0
C8
DQ1
C2
DQ2
D7
DQ3
D3
DQ4
D1
DQ5
D9
DQ6
B1
DQ7
B9
DQS
B7
DQS
A8
DM/RDQS
B3
NU/RDQS
A2
VDDQ_1
A9
VDDQ_2
C1
VDDQ_3
C3
VDDQ_4
C7
VDDQ_5
C9
VDD_1
A1
VDD_2
L1
VDD_3
E9
VDD_4
H9
VSSQ_1
A7
VSSQ_2
B2
VSSQ_3
B8
VSSQ_4
D2
VSSQ_5
D8
VSS_1
A3
VSS_2
E3
VSS_3
J 1
VSS_4
K9
VREF
E2
VDDL
E1
VSSDL
E7
0.1uF
C427
OPT
0.1uF
C
4
2
8
OPT
DDR1_VREF0
DDR0_VREF0
0
R415
0
R414
LGE3556CP (C0 3D PIP)
IC100
DDR_BVDD0
A6
DDR_BVDD1
A24
DDR_BVSS0
B7
DDR_BVSS1
B24
DDR_PLL_TEST
F20
DDR_PLL_LDO
B23
DDR01_CKE
B17
DDR_COMP
C22
DDR01_ODT
E16
DDR_EXT_CLK
C23
DDR0_CLK
B12
DDR0_CLKB
C12
DDR1_CLK
A13
DDR1_CLKB
A12
DDR01_A00
B15
DDR01_A01
E14
DDR01_A02
A15
DDR01_A03
D15
DDR0_A04
E13
DDR0_A05
E12
DDR0_A06
F13
DDR01_A07
C14
DDR01_A08
F14
DDR01_A09
B14
DDR01_A10
D14
DDR01_A11
C13
DDR01_A12
D13
DDR01_A13
B13
DDR1_A04
F15
DDR1_A05
C15
DDR1_A06
D16
DDR01_BA0
F16
DDR01_BA1
B16
DDR01_BA2
E15
DDR01_CASB
A17
DDR0_DQ00
A8
DDR0_DQ01
B11
DDR0_DQ02
B8
DDR0_DQ03
D11
DDR0_DQ04
E11
DDR0_DQ05
C8
DDR0_DQ06
C11
DDR0_DQ07
C9
DDR0_DQ08
D8
DDR0_DQ09
E10
DDR0_DQ10
E9
DDR0_DQ11
F11
DDR0_DQ12
F12
DDR0_DQ13
E8
DDR0_DQ14
D10
DDR0_DQ15
F8
DDR1_DQ00
C18
DDR1_DQ01
C20
DDR1_DQ02
A18
DDR1_DQ03
B21
DDR1_DQ04
C21
DDR1_DQ05
B18
DDR1_DQ06
B20
DDR1_DQ07
D18
DDR1_DQ08
E18
DDR1_DQ09
D21
DDR1_DQ10
F18
DDR1_DQ11
E20
DDR1_DQ12
A22
DDR1_DQ13
F17
DDR1_DQ14
B22
DDR1_DQ15
E17
DDR0_DM0
A10
DDR0_DM1
C10
DDR1_DM0
A20
DDR1_DM1
F19
DDR0_DQS0
B10
DDR0_DQS0B
B9
DDR0_DQS1
F10
DDR0_DQS1B
F9
DDR1_DQS0
B19
DDR1_DQS0B
C19
DDR1_DQS1
E19
DDR1_DQS1B
D19
DDR01_RASB
C16
DDR_VREF0
A7
DDR_VREF1
A23
DDR01_WEB
C17
DDR_VDDP1P8_1
C7
DDR_VDDP1P8_2
D22
10uF
16V
C425
10uF
16V
C426
DDR01_A[12]
DDR01_A[0]
DDR01_A[8]
DDR0_A[6]
DDR1_DQ[15]
DDR01_A[1]
DDR1_DQ[7]
DDR01_A[2]
DDR01_A[2]
DDR01_A[9]
DDR01_A[1]
DDR1_DQ[0]
DDR1_DQ[5]
DDR0_DQ[7]
DDR1_DQ[11]
DDR1_DQ[8]
DDR01_A[10]
DDR0_DQ[6]
DDR1_A[5]
DDR0_DQ[9]
DDR01_A[12]
DDR1_DQ[7]
DDR01_A[3]
DDR1_DQ[15]
DDR0_A[6]
DDR1_DQ[9]
DDR1_A[5]
DDR0_DQ[5]
DDR01_A[7]
DDR0_DQ[10]
DDR01_A[10]
DDR1_DQ[8]
DDR01_A[11]
DDR1_DQ[4]
DDR0_DQ[11]
DDR0_A[4]
DDR1_DQ[0]
DDR1_A[5]
DDR0_DQ[4]
DDR01_A[7]
DDR0_A[5]
DDR01_A[1]
DDR0_DQ[1]
DDR0_DQ[2]
DDR1_DQ[14]
DDR01_A[7]
DDR01_A[8]
DDR01_A[0]
DDR01_A[2]
DDR0_A[5]
DDR1_A[4]
DDR01_A[3]
DDR0_A[6]
DDR0_A[6]
DDR1_DQ[13]
DDR01_A[13]
DDR01_A[10]
DDR1_A[6]
DDR1_A[4]
DDR01_A[11]
DDR0_DQ[5]
DDR01_A[3]
DDR01_A[9]
DDR0_DQ[7]
DDR01_A[0]
DDR1_A[6]
DDR0_DQ[10]
DDR01_A[2]
DDR1_DQ[5]
DDR01_A[8]
DDR0_DQ[4]
DDR01_A[12]
DDR01_A[1]
DDR0_DQ[14]
DDR01_A[12]
DDR01_A[9]
DDR01_A[9]
DDR0_DQ[14]
DDR01_A[3]
DDR01_A[13]
DDR01_A[12]
DDR0_DQ[13]
DDR01_A[7]
DDR0_DQ[11]
DDR01_A[10]
DDR1_DQ[10]
DDR01_A[9]
DDR01_A[10]
DDR1_DQ[12]
DDR0_A[5]
DDR0_DQ[2]
DDR01_A[7]
DDR0_DQ[3]
DDR1_DQ[4]
DDR01_A[11]
DDR1_DQ[2]
DDR1_DQ[13]
DDR1_A[4]
DDR01_A[8]
DDR0_DQ[0]
DDR1_DQ[1]
DDR01_A[0]
DDR01_A[11]
DDR01_A[11]
DDR01_A[0]
DDR0_A[4]
DDR01_A[10]
DDR01_A[12]
DDR1_A[6]
DDR01_A[11]
DDR0_A[4]
DDR01_A[2]
DDR01_A[13]
DDR01_A[0]
DDR1_DQ[10]
DDR1_DQ[14]
DDR0_DQ[9]
DDR1_DQ[1]
DDR01_A[3]
DDR1_A[6]
DDR0_A[4]
DDR0_DQ[15]
DDR01_A[8]
DDR01_A[10]
DDR01_A[11]
DDR01_A[1]
DDR0_DQ[15]
DDR1_DQ[12]
DDR01_A[13]
DDR0_DQ[12]
DDR1_DQ[3]
DDR0_DQ[1]
DDR01_A[8]
DDR0_DQ[8]
DDR1_DQ[11]
DDR0_DQ[12]
DDR01_A[7]
DDR01_A[13]
DDR01_A[7]
DDR0_DQ[0]
DDR0_DQ[8]
DDR0_DQ[13]
DDR01_A[13]
DDR1_DQ[2]
DDR1_DQ[9]
DDR1_DQ[6]
DDR01_A[1]
DDR1_A[5]
DDR01_A[13]
DDR0_DQ[3]
DDR01_A[2]
DDR01_A[2]
DDR01_A[0]
DDR1_DQ[3]
DDR01_A[12]
DDR0_DQ[6]
DDR01_A[9]
DDR1_DQ[6]
DDR01_A[9]
DDR01_A[3]
DDR01_A[8]
DDR01_A[3]
DDR01_A[1]
DDR0_A[5]
DDR1_A[4]
4
HONG YEON HYUK
C l o s e t o I C
C l o s e t o I C
C l o s e t o I C
C l o s e t o I C
S I
S I
P I
* DDR_VTT
2 0 0 9 . 0 6 . 1 8
DDR Memory
BCM (EUROBBTV)
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
+3.3V_NORMAL
100
R1701
M_REMOTE_RX
9 : F 3 ; 9 : G 4
M_REMOTE_TX
9 : F 3 ; 9 : G 4
100
R1702
BLM18PG121SN1D
120-ohm
L1700
2.7K
R1705
+3.3V_NORMAL
100
R1700
M_RFModule_RESET
9 : F 3 ; 9 : G 4
DC
9 : F 3 ; 9 : G 3
100
R1703
100
R1704
DD
9 : F 3 ; 9 : G 3
2.7K
R1706
2.7K
R1707
12507WS-08L
M_REMOTE
P1700
1
2
3
4
5
6
7
8
9
M o t i o n R e m o c o n I n t e r f a c e
M o t i o n R e m o t e c o n t r o l l e r
ALL M_REMOTE OPTION
0 9 / 1 0 / x x
MOTION_REMOCON
2 0 1 0 0
GP2_BCM_ATSC
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
33
R2727
ISA1530AC1
Q2701
E
B
C
TU_CVBS
33
R2729
2.2K
R2740
AZ2940D-2.5TRE1
IC2700
2
GND
3
VOUT
1
VIN
18pF
50V
50V
C2714
TU_SIF
NR8040T3R6N
3.6uH
L2704
SDA2_3.3V
0 . 1 u F
16V
C2702
FE_TS_ERR
0 . 1 u F
16V
C2734
200
R2702
0 . 1 u F
16V
16V
C2726
1uF
10V
C2717
100pF
50V
50V
C2705
FE_TS_VAL_ERR
0
R2736
18pF
50V
50V
C2712
0 . 1 u F
16V
C2736
33
R2728
10K
R2755
ISA1530AC1
Q2702
E
B
C
82
R2749
MP2212DN
IC2701
3
IN
2
GND
4
BS
1
FB
5
VCC
6
SW_1
7
SW_2
8
EN/SYNC
IF_AGC_SEL
100pF
50V
50V
C2700
10K
R2742
+2.5V_TU
+5V_TU
0 . 1 u F
16V
C2719
ISA1530AC1
Q2705
E
B
C
0 . 1 u F
16V
16V
C2720
0 . 1 u F
C2731
NL17SZ08DFT2G
IC2702
3
2
4
1
5
SCL2_3.3V
+1.2V_TU
100pF
50V
50V
C2704
10pF
50V
50V
C2711
+5V_TU
+3.3V_TU
+5V_NORMAL
LNA2_CTL/BOSTER_CTL
0 . 1 u F
16V
16V
C2701
200
R2712
100
R2721
22uF
10V
C2729
+5V_TU
+1.2V_TU
2SC3052
OPT
Q2700
E
B
C
+3.3V_TU
0 . 1 u F
16V
C2721
SDA0_3.3V
+5V_TU
0
R2719
22uF
10V
C2728
+3.3V_TU
33
R2726
POWER_ON/OFF2_2
0 . 1 u F
16V
C2706
0
R2738
10K
R2732
22K
1%
R2731
+3.3V_NORMAL
0
R2720
4.7K
R2743
200
R2741
BLM18PG121SN1D
L2700
10pF
50V
50V
C2713
22uF
10V
C2730
FE_TS_VAL
10K
OPT
R2724
BLM18PG121SN1D
L2701
10uF
10V
10V
C2723
47
R2758
+5V_TU
1/10W
10
1%
R2718
2SC3052
Q2703
E
B
C
+3.3V_TU
0 . 1 u F
16V
C2725
+3.3V_TU
ISA1530AC1
Q2704
E
B
C
18K
1%
R2756
0 . 1 u F
16V
C2724
SCL0_3.3V
TUNER_RESET
0 . 1 u F
16V
C2733
0 . 1 u F
16V
16V
C2703
1/8W
75K
1%
R2713
200
R2739
100pF
50V
50V
C2716
470
R2746
100K
R2723
+3.3V_TU
0 . 1 u F
16V
C2707
10uF
10V
10V
OPT
C2709
CIC21J501NE
L2703
CIC21J501NE
L2702
0
OPT
R2700
+5V_TU
22uF
10V
10V
C2715
0 . 1 u F
16V
C2710
0 . 0 1 u F
25V
25V
C2718
+2.5V_TU
ATV_OUT
1
R2744
0 . 1 u F
16V
16V
OPT
C2708
0 . 1 u F
16V
C2722
TDFR-G155D
VERTICAL_NIM
TU2701
1
RF_S/W_CNTL
2
BST_CNTL
3
+B1[5V]
4
NC[RF_AGC]
5
AS
6
SCL[A_DEMOD]
7
SDA[A_DEMOD]
8
NC(IF_TP)
9
S I F
10
NC
11
VIDEO
12
GND
13
1.2V
14
3.3V
15
RESET
16
2.5V
17
SCL[D_DEMOD]
18
SDA[D_DEMOD]
19
ERR
20
SYNC
21
VALID
22
MCL
23
D0
24
D1
25
D2
26
D3
27
D4
28
D5
29
D6
30
D7
31
SHIELD
22uF
10V
10V
C2737
FE_TS_SERIAL
0
R2725
FE_TS_SYNC
FE_TS_ERR
FE_TS_DATA_CLK
FE_TS_DATA[0-7]
FE_TS_VAL
47
R2710
47
R2716
47
R2757
47
R2706
47
R2711
47
R2703
47
R2705
47
R2709
47
R2708
47
R2717
47
R2704
47
R2707
TDFR-G055D
TU2701-*1
VERTICAL_NIM_T2
1
RF_S/W_CNTL
2
BST_CNTL
3
+B1[5V]
4
NC[RF_AGC]
5
AS
6
SCL[A_DEMOD]
7
SDA[A_DEMOD]
8
NC(IF_TP)
9
S I F
10
NC
11
VIDEO
12
GND
13
1.2V
14
3.3V
15
RESET
16
2.5V
17
SCL[D_DEMOD]
18
SDA[D_DEMOD]
19
ERR
20
SYNC
21
VALID
22
MCL
23
D0
24
D1
25
D2
26
D3
27
D4
28
D5
29
D6
30
D7
31
SHIELD
10uF
16V
C2727
TC7SZ02FU
VERTICAL_NIM_T2
I C 2 7 0 2 - * 1
3
GND
2
IN_A
4
OUT_Y
1
IN_B
5
VCC
22uF
10V
C2735
FE_TS_DATA[3]
FE_TS_DATA[2]
FE_TS_DATA[4]
FE_TS_DATA[7]
FE_TS_DATA[1]
FE_TS_DATA[6]
FE_TS_DATA[0]
FE_TS_DATA[5]
27
close to TUNER
60mA
CAN H-NIM/NIM TUNER for EU
200mA
close to TUNER
C l o s e t o I C
R2
OPTION : RF AGC
3A
$ 0 . 1 1
R1
V o u t = 0 . 8 * ( 1 + R 1 / R 2 )
close to TUNER
C l o s e t o t h e t u n e r
O n l y U s e T 2 f o r C I
r ( F u l l N i m )
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
REAR_AV_L_IN
REAR_AV_R_IN
REAR_AV_CVBS
JACK_REAR_AV_LR_INCM
002:C6
JACK_AV_CVBS_INCM
10K
R3328
+3.3V_NORMAL
100pF
50V
50V
C3309
1K
R3326
REAR_AV_DET
9 : G 5 ; 8 5 : N 2 3
0 . 1 u F
C8331
DPRX_ML_L0N
0 . 1 u F
C3305
DPRX_ML_L1P
DPRX_ML_L1N
PANEL_CTL
1/16W
10K
5%
R3308
0 . 1 u F
C3307
0
R3312
OPT
0 . 1 u F
C3306
0 . 1 u F
C3303
+3.5V_ST
0 . 1 u F
C3304
DPRX_ML_L0P
POWER_CTRL_24V
DPRX_AUX_N
DPRX_AUX_P
SDA3_3.3V
SCL3_3.3V
DP_CABLE_DET
5.5V
D3300
LG5111_RESET
PWM_DIM
INV_CTL
FRC_RESET
33
R3305
BCM_GPIO
0
R3306
L/R_SYNC
232C_TXD
COMP1_Pr
JACK_COMP1_VID_INCM
COMP1_Pb
COMP1_Y
+3.3V_NORMAL
10K
R3327
1K
R3325
COMP1_DET
9 : F 5 ; 9 : G 5
100pF
50V
C3308
232C_RXD
0
R3330
0
R3331
OPT
INV_CTL_TR
TF05-51S
P3302
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
RGB_DDC_SCL
SPDIF_OUT
DSUB_5V
PC_R_IN
JACK_R_VID_INCM
+3.3V_NORMAL
JACK_PC_LR_INCM
DSUB_HSYNC
DSUB_G
RGB_DDC_SDA
DSUB_VSYNC
DSUB_R
DSUB_B
PC_L_IN
JACK_B_VID_INCM
JACK_G_VID_INCM
DSUB_DET
TF05-41S
P3301
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
E_TMS
E_TDI
E_TCK
E_TDO
0
R3332
NORMAL_I2C
0
R3333
NORMAL_I2C
0
TCON_FPGA_DL
R3334
0
TCON_FPGA_DL
R3335
0 BCM_GPIO
R3336
0
TCON_FPGA_DL
R3337
0
TCON_FPGA_DL
R3338
75
R3339
75
R3340
75
R3341
RCLAMP0544T.TCT
AD1
1
8
2
7
3
6
4
5
9
RCLAMP0544T.TCT
AD2
1
8
2
7
3
6
4
5
9
30V
D3301
30V
D3302
30V
D3306
30V
D3310
30V
D3304
30V
D3308
30V
D3303
30V
D3305
30V
D3309
Jack Board WAFER
1 0 / 0 1 / x x
J a c k B / D w a f e r
3 3 1 0 0
GP2_BCM_ATSC
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