LG 55EA9800-SA (CHASSIS:EJ34D) Service Manual ▷ View online
H13 Block diagram
DIF
TS (P)
System
D
Global Baseband
H13A
H13D
Video Decoder
Multi-STD
UART 3
TS(P)
TS(P)
GBB AFE
1ch@30MHz
DVB-CI/CI+
TS(S)
GPU Rogue Han
USB2.0x3
TS(S)
SDRAM
(MCP)
Tuner
Demux
Audio DSP
Multi-STD
Audio Decoder
LX4 HiFi EP
SIF
Global Baseband
V/Q, DVB-T/C ISDB-T
AAD
(THAT)
Mux
I2S(External)
Multi STD
HD Decoder
(Boda950)
Audio
2D GFX
JPG/PNG Decoder
JPG Encoder
UARTx3
EMAC
SCI
SPIx2
I2Cx10
PHY
1ch@30MHz
w/ PLL
BTSC AFE
10b@18.432MHz
w/ PLL
Video Encoder
1080p@30fps
GPIOx136
Audio L/R(4-ch)
SCART out
SW
Audio DAC (48KHz)
Line Out
TrustZone
CPU
ARMCA9 Core
Dual 1.2GHz
Sound DSP
Clear Voice II
Perceptual
Volume Control
I2S
I2S(HPD)
CPU
64KB SRAM
48KB ROM
OTP
I2Cx10
eMMC
DMAC(8ch)
Timer
WDT
1ch L/R
Audio-ADC
24b@48KHz
USB3.0 x1
Secure Engine
Audio DAC
(48KHz )
I2S
I2S
SW
CVBS(3ch)
CVBS
Encoder
32KBI$
32KBD$
1MB L2 $
Slim SPK
DivX
Bluetooth
Digital AMP
I2S(HPD)
SPDIF
UART
OTP
Timer
SRAM 16KB
Digital
Audio
Output
CVBS DAC
5x1ch (1ch)
Component(2ch)
CVBS AFE(2-ch)
12b@54MHz
CVBS-Out
Mu
x
10x3ch
DE
Encoder
LVDS
Tx
e Mu
x
R
e
rlac
er
b Scale
r
D
C
R
SW
SW
3ch Video
AFE
10b@148.5MHz
LVDS
Rx
CVD
Y/C
CVBS
BE
D
R
C
R
E
E
1
S
D
D
o
rmatter
O
N
MCU
Capture
Block
(3CH)
Mu
x
/E
P
I/
L
VDS C
omb
o
(120Hz
)
MCU
HDMI-Rx 1.4
(1-port PHY)
DDR3 Controller
Audio PLL
w/ DCO
Sourc
e
TN
De-int
e
Ma
in
/Su
b
H3
V
C
w/ LLPLL
I2Cx1
H3
DDR3 Controller
SPLL
DDR
DPLL
DDR
F
R
S
R
P
E
O
S
LE
Output f
o
TC
O
(3CH)
I2Cx1
HDMI
(1-Link)
HDMI
Vx1
/
CPLL
DCO
x2
GPIOIx16
3D, ARC, 4kx2k
DDR3 PHY
DDR3 PHY
DDR
PLL
DDR
PLL
16
16
16
16
H13 Block diagram
H13 Block diagram
+3.3V D Demod
[+3.3V_TUNER] 5
[+.1.8V_TUNER] 7
+1.23V_D_Demod
[+3.3V_S2_DEMOD] 32
+3.3V_NORMAL
3 3K Ω
+1.8_TU
+3.3V_TU
_ _
[+1.23V_S2_DEMOD] 30
LNB_TX
LNB
IC6900
A8303SESTR-TB
10 [TONECTRL]
2 [LNB]
7 [SCL]
8 [SDA]
[S2_F22_OUTPUT] 33
[LNB] 36
[S2_SCL] 34
[S2_SDA] 35
I2C_SCL4
I2C_SDA4
I2C_SDA4
22 Ω
LNB_OUT
3.3K Ω
TU6503
H13
[RESET] 2
/TU_RESET1
AG6 [GPIO10]
IC2_SCL6
IC2 SDA6
AH34 [SCL5]
[SLC] 3
[T/C_DIF[N]] 11
AP6 [SCL3]
AR6 [SDA3]
AR6 [SDA3]
33 Ω
TU6503
TDSQ-H651F
H13
LG1154D
IC2_SDA6
AH33 [SDA5]
[SDA] 4
[ERROR] 16
[SYNC] 17
[VALID] 18
[MCLK] 19
AL37 [TP_DVB_ERR]
AL36 [TP_DVB_SOP]
AL35 [TP_DVB_VAL]
AM36 [TP_DVB_CLK]
AL36 [TP_DVB_SOP]
AL35 [TP_DVB_VAL]
AM36 [TP_DVB_CLK]
FE_DEMOD1_TS_ERROR
FE_DEMOD1_TS_SYNC
FE_DEMOD1_TS_VAL
FE_DEMOD1_TS_CLK
FE_DEMOD1_TS_SYNC
FE_DEMOD1_TS_VAL
FE_DEMOD1_TS_CLK
[D0] 20
[D1] 21
[D2] 22
[D3] 23
[D4] 24
[D5] 25
[D6] 26
[D7] 27
[D1] 21
[D2] 22
[D3] 23
[D4] 24
[D5] 25
[D6] 26
[D7] 27
FE_DEMOD1_TS_DATA [0-7]
AM35 [TP_DVB_DATA0]
AN36 [TP_DVB_DATA1]
AN37 [TP_DVB_DATA2]
AN35 [TP_DVB_DATA3]
AP37 [TP_DVB_DATA4]
AP36 [TP_DVB_DATA5]
AR37 [TP_DVB_DATA6]
AR37 [TP DVB DATA7]
AN36 [TP_DVB_DATA1]
AN37 [TP_DVB_DATA2]
AN35 [TP_DVB_DATA3]
AP37 [TP_DVB_DATA4]
AP36 [TP_DVB_DATA5]
AR37 [TP_DVB_DATA6]
AR37 [TP DVB DATA7]
[D7] 27
AR37 [TP_DVB_DATA7]
[S2_RESET] 31
/S2_RESET
AG5 [GPIO9]
[T/C_DIF[P]] 10
[T/C_DIF[N]] 11
FILTER
H13
LG1154A
IF_P
IF_N
TUNER_SIF
TU_CVBS
IF_AGC
U17 [ADC_I_INP]
V17 [ADC_I_INN]
ADC_I_INP
ADC_I_INN
H13 Block diagram
[CVBS IN3]
AV1_CVBS_IN
AV1
Phone JACK
AV1_CVBS_IN_SOC
Jack Side
SOC Side
[CVBS_IN3]
FULL
SCART
(18P)
SC_CVBS_IN
[CVBS IN2]
SC_CVBS_IN_SOC
[AUAD_L/R_CH2_IN]
AV_L/R_IN
AUAD_L/R_CH2_IN
H13
[CVBS_IN2]
SC_R/G/B
/CVBS_IN_SOY
/CVBS_IN_SOY
COMP1_PR_IN_SOC
COMP1_Y_IN_SOC
COMP1 PB IN SOC
COMP1_Y_IN_SOC
COMP1 PB IN SOC
[PR1/Y1/PB1/SOY1_IN]
H13
(LG1154A)
[AUAD_L/R_CH3_IN]
COMP1_PB_IN_SOC
COMP1_Y_IN_SOC_SOY
COMP1_Y_IN_SOC_SOY
SC_L/R_IN
AUAD_L/R_CH3_IN
COMP1_Y/Pb/Pr
Component 1
Phone JACK
COMP2_PB_IN_SOC
COMP2_Y_IN_SOC
COMP2_Y_IN_SOC
[PB2/Y2/SOY2/PR2_IN]
COMP2_Y_IN_SOC_SOY
COMP2_PR_IN_SOC
COMP2_PR_IN_SOC
Tuner
TU_CVBS_IN
TU_CVBS_IN_SOC
[CVBS_IN1]
SIF
DIF[P/N]
DIF[P/N]
TUNER_SIF
ADC_I_INP/INN
ADC_I_INP/INN
[AAD_ADC_SIF]
[ADC I INP/INN]
[ADC I INP/INN]
[
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