LG 50PX950-AA (CHASSIS:PA02B) Service Manual ▷ View online
Block Diagram - Overview
TAS5709
(Digital AMP)
SOC_Reset
CVBS/L/R
R/G/B, H/V Sync
RGB-PC
HDMI
1/2/3/4
SPDIF OUT
I2S
BCM3556
MCLK
HDMI CEC
HDMI CEC
(To Micom)
IR
Buffer
Buffer
USB2.0
Y/Cb/Cr/L/R
USB2512
USB2512
Bluetooth
PC audio in
DP/DM
DP/DM
RMII
RMII
RS-232C
UART
I2C
DDC
(26Pin
)
TV_CVBS
SIF
RF Jack
RF Jack
X-tal
(54MHz)
NAND
Flash(4G)
DDR(1GBit)x4
24C01
SYSTEM
SYSTEM
EEPROM
EEPROM
Half-NIM
TMDS/DDC
TMDS/DDC
TMDS/DDC
TMDS/DDC
24C16
24C16
Local
Local
KEY
KEY
IF
DP/DM
NEC
NEC
Micom
Micom
8Bits
8Bits
Component1/2
B/T_HP_LOUT_AMP
Wireless interface
I2C, Detect,
RX/TX,IR
12P
NEC ISP
NEC ISP
IC103
X-tal
(10MHz)
HDMI
HDMI
Switch
Switch
TMDS/DDC
I2C
AV1/2
3D SYNC_IR EMITTER
3D_SYNC_OUT
Main board (GP2 modify)
Changed Point
1. BCM 3556 revision
-
BCM3556 -> BCM3556CP
- Change the BCM version to support HDMI1.4a 3D
2. Add IR emitter wafer
- IR signal from ASIC to Main through the LVDS cable.
- IR assy connect to 4pin wafer on the main board.
- IR assy connect to 4pin wafer on the main board.
3. Another block is almost same as GP2 chassis
BCM3556CP
DDR
DDR
HDMI
MUX
HDMI
HDMI
HDMI
RS232
RGB
LAN
Tuner
USB
USB
HDMI
PC Audio
SPDIF
Rear AV
Component
Side AV
Power 18pin
IR emitter 4pin
Center LED 3pin
LVDS
IR/Control
wireless
Speaker 4pin
IR emitter assy - front
IR emitter assy - back
Main board for 3D image
Main board for 3D block diagram
Motion Remocon
3D Formatter Board (3DF)
DDR
DDR
L
V
DS to ASIC
L
V
DS from
M
a
in
FPGA
3D
FPGA
2D to 3D
3D formatter board image
3D formatter board layout
3D
chip
BCM
Module
(ASIC)
L
R
L
R
3D Source
3D
R
L
2D
2D
2D Source
3D
R
L
BCM
2D to 3D
chip
3D
chip
L
R
Module
(ASIC)
3D function
2D to 3D function
2D to 3D
chip
L
R
Bypass
3DF board
3DF board
2D to 3D chip
3D chip
2D to 3D D/L wafer
3D D/L wafer
Block Diagram – 3DF B/D
(PDP 3DTV)
LVDS (51P
in)
BCM
I2C
L/R DETECT
FPGA RESET
LVDS 2Ch
I2C
L/R DETECT
FPGA RESET
LVDS 2Ch
X-tal
(54MHz)
DDR2
(512Mbitx2)
PROM
(16Mbit)
2D to 3D
Converter
(FPGA)
EP3C55F484
3D Formatter
(FPGA)
EP3C55F484
I2C
FPGA RESET
LVDS 2Ch
X-tal
(54MHz)
PROM
(16Mbit)
LVDS 2Ch
(
Left
)
LVDS (80P
in)
LVDS 2Ch
(
Right
)
3D
_S
YN
C
3D_SYNC
■ Input
1 LVDS RX (2 channel)
10 bit 1920x1080p@60Hz
10 bit 1920x1080p@60Hz
■ Output
2 LVDS TX (4 channel)
10 bit 1920x1080p@120Hz
10 bit 1920x1080p@120Hz
■ Processing
148.5 MHz, 74.24 MHz
DDR2 IF(153MHz)
CSC (RGB ÅÆ YUV) included
Scaler included
I2C input from LVDS RX
DDR2 IF(153MHz)
CSC (RGB ÅÆ YUV) included
Scaler included
I2C input from LVDS RX
5V_VCC
5V_VCC
3D_SYNC
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