LG 47SL9000-ZA / 47SL9500-ZB (CHASSIS:LD91L) Service Manual ▷ View online
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
+3.3V_MEMC
BLM18PG121SN1D
L902
+1.8V_FRC_DDR
MEMC_RXE1+
MEMC_RXE1-
MEMC_RXE3+
MEMC_RXE2+
MEMC_RXE3-
MEMC_RXE2-
MEMC_RXO0-
MEMC_RXEC+
MEMC_RXO1-
MEMC_RXO1+
MEMC_RXE4+
MEMC_RXO0+
MEMC_RXEC-
MEMC_RXE4-
MEMC_RXO4-
MEMC_RXO3+
MEMC_RXOC-
MEMC_RXOC+
MEMC_RXO2+
MEMC_RXO4+
MEMC_RXO3-
MEMC_RXO2-
PANEL_POWER
BIT_SEL
+3.3V_MEMC
+3.3V_MEMC
+3.3V_MEMC
MEMC_RESET
URSA_RASZ
URSA_CASZ
URSA_WEZ
URSA_BA1
URSA_BA0
URSA_MCLKE
URSA_DQM1
URSA_DQM0
URSA_DQS0
URSA_DQSB0
URSA_DQS1
URSA_DQSB1
URSA_MCLK1
URSA_MCLKZ1
URSA_DQM3
URSA_DQM2
URSA_DQS2
URSA_DQSB2
URSA_DQS3
URSA_DQSB3
URSA_MCLK
URSA_MCLKZ
URSA_ODT
URSA_DQ[0-31]
URSA_A[0-12]
M_XTALI
M_XTALO
M_XTALO
M_XTALI
M_SPI_CZ
M_SPI_DO
M_SPI_CK
M_SPI_DI
M_SPI_CZ
M_SPI_DO
M_SPI_DI
M_SPI_CK
+3.3V_MEMC
820
R954
100
R930
100
R943
100
R938
100
R946
100
R935
100
R945
100
R929
100
R942
100
R936
100
R928
MEMC_SDA
MEMC_SCL
BLM18PG121SN1D
L904
BLM18PG121SN1D
L905
MEMC_RXE0+
MEMC_RXE0-
10uF
C913
10uF
C917
10uF
C914
10uF
10V
C916
10uF
1
0
V
C908
22uF
16V
C909
22uF
16V
C912
W25X20AVSNIG
IC902
3
WP
2
DO
4
GND
1
CS
5
DIO
6
CLK
7
HOLD
8
VCC
+3.3V_MEMC
100
R992
100
R993
+3.3V_MEMC_AVDD
+3.3V_MEMC
+3.3V_MEMC
+3.3V_MEMC
12MHz
X900
CB3216PA501E
L907
PWM_DIM
OPC_EN
OPC_OUT1
10uF
C907
OPC_OUT2
LVDS_SEL
+1.26V_MEMC
WP_FLASH_MEMC
1M
R934
100
R931
100
R939
+3.3V_MEMC_AVDD
WP_FLASH_MEMC
1K
R941
OPT
1K
R956
1K
R940
OPT
+3.3V_MEMC
1K
R957
MEMC_SDA
0 0 1 : E 2 0 ; 0 1 1 : I 2 2
MEMC_SCL
0 0 1 : E 2 0 ; 0 1 1 : I 2 2
12507WR-04L
P902
OPT
1
2
3
4
5
0
R953
0
OPT
R933
0
R979
0
OPT
R973
0
R971
OPT
0
R937
OPT
22 OPT
R955
22
OPT
R967
4.7K
R978
OPT
4.7K
OPT
R970
4.7K
OPT
R972
0.1uF
C903
0.1uF
C956
0.1uF
C904
0 . 1 u F
C953
0.1uF
C918
0 . 1 u F
C935
0 . 1 u F
C932
0.1uF
C938
0 . 1 u F
C950
0.1uF
C941
0 . 1 u F
C934
0 . 1 u F
C919
0 . 1 u F
C949
0 . 1 u F
C947
0 . 1 u F
C920
0.1uF
C937
0.1uF
C944
0 . 1 u F
C923
0 . 1 u F
C929
0 . 1 u F
C928
0 . 1 u F
C925
0 . 1 u F
C936
0 . 1 u F
C927
0.1uF
C939
0.1uF
C945
0 . 1 u F
C926
0 . 1 u F
C933
0 . 1 u F
C922
0 . 1 u F
C921
1000pF
C952
10K
R927
10K
R951
10K
R952
10K
R994
1K
R960
OPT
1K
R959
1K
R964
OPT
1K
R963
1K
R949
1K
R950
OPT
1uF
C924
1uF
C906
56
R925
56
R947
56
R948
56
R926
TF05-51S
P900
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
TF05-41S
P901
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
0.1uF
C957
OPT
0.1uF
C958
OPT
0.1uF
C959
OPT
BLM18PG121SN1D
L908
OPT
BLM18PG121SN1D
L909
BLM18PG121SN1D
L910
BLM18PG121SN1D
L911
0.1uF
C960
OPT
0.1uF
C961
OPT
0.1uF
C962
OPT
0.1uF
C963
OPT
0.1uF
C964
OPT
BLM18PG121SN1D
L903
10uF
1
0
V
C901
10uF
10V
C905
[ E 1 ]
[ D 1 ]
[ L 9 ]
[ N 5 ]
[ N 4 ]
[ N 1 2 ]
[ N 1 3 ]
LGE7329A
IC900
E1
SDAS
D1
SCLS
F1
GPIO[8]
G1
GPIO[9]
K8
GND_14
E5
VDDC_1
E2
GPIO[10]
F2
GPIO[11]
F3
GPIO[12]
G2
GPIO[13]
M4
GPIO[22]
M5
GPIO[23]
G3
GPIO[14]
E4
GPIO[15]
F4
GPIO[16]
G4
GPIO[17]
H4
GPIO[18]
J 4
GPIO[19]
K4
GPIO[20]
L4
GPIO[21]
J 6
VDDP_2
H9
GND_7
F6
VDDC_2
H1
MDATA[20]
H2
MDATA[19]
H3
MDATA[17]
J 1
MDATA[22]
J 2
MDATA[27]
J 3
MDATA[28]
K1
MDATA[25]
K2
MDATA[30]
K6
AVDD_DDR_2
K3
DQM[3]
L1
DQM[2]
J 8
GND_10
L2
DQS[2]
L3
DQSB[2]
L6
AVDD_DDR_4
L8
VDDP_3
H10
GND_8
M1
DQS[3]
M2
DQSB[3]
L7
AVDD_DDR_5
M3
MDATA[31]
N1
MDATA[24]
J 9
GND_11
N2
MDATA[26]
N3
MDATA[29]
L10
AVDD_DDR_6
P1
MDATA[23]
R1
MDATA[16]
T1
MDATA[18]
T2
MDATA[21]
R2
MCLK[0]
P2
MCLKZ[0]
G7
GND_1
L9
AVDD_MEMPLL
N5
MVREF
N4
ODT
T3
RASZ
R3
CASZ
P3
MADR[0]
T4
MADR[2]
R4
MADR[4]
J10
GND_12
P4
MADR[6]
T5
MADR[8]
R5
MADR[11]
P5
WEZ
T6
BADR[1]
R6
BADR[0]
P6
MADR[1]
T7
MADR[10]
L11
AVDD_DDR_7
R7
MADR[5]
P7
MADR[9]
T8
MADR[12]
R8
MADR[7]
P8
MADR[3]
N8
MCLKE
K10
GND_16
F7
VDDC_3
T9
MDATA[4]
R9
MDATA[3]
K7
GND_13
P9
MDATA[1]
T10
MDATA[6]
K11
AVDD_DDR_3
R10
MDATA[11]
P10
MDATA[12]
T11
MDATA[9]
R11
MDATA[14]
J11
AVDD_DDR_1
P11
DQM[1]
T12
DQM[0]
R12
DQS[0]
P12
DQSB[0]
H11
VDDP_1
T13
DQS[1]
R13
DQSB[1]
P13
MDATA[15]
T14
MDATA[8]
R14
MDATA[10]
P14
MDATA[13]
T15
MDATA[7]
R15
MDATA[0]
P15
MDATA[2]
T16
MDATA[5]
R16
MCLK[1]
P16
MCLKZ[1]
N9
GPIO[26]
N10
GPIO[27]
N11
GND_17
M11
RESET
G6
VDDC_4
N12
GPIO[28]
N13
GPIO[29]
N14
GPIO[30]
L13
SCK
M13
SDI
M12
SDO
K13
CSZ
L12
PWM1
K12
PWM0
J 1 3
GPIO[0]
H13
GPIO[1]
G13
GPIO[2]
F13
GPIO[3]
E13
GPIO[4]
F12
GPIO[5]
D14
GPIO[6]
E12
GPIO[7]
N6
GPIO[24]
H6
VDDC_5
N15
LVD4M
N16
LVD4P
M14
LVD3M
M15
LVD3P
F8
AVDD_33_1
M16
LVDCKM
L16
LVDCKP
L15
LVD2M
L14
LVD2P
G9
GND_3
K14
LVD1M
J 1 4
LVD1P
J 1 6
LVD0M
J 1 5
LVD0P
H15
LVC4M
H16
LVC4P
H14
LVC3M
G14
LVC3P
G16
LVCCKM
G15
LVCCKP
F15
LVC2M
F16
LVC2P
F14
LVC1M
E14
LVC1P
E16
LVC0M
E15
LVC0P
G10
GND_4
F9
AVDD_33_2
D16
LVB4M
D15
LVB4P
C16
LVB3M
B16
LVB3P
A16
LVBCKM
A15
LVBCKP
B15
LVB2M
C15
LVB2P
D2
GPIO_3
E3
GPIO_10
E10
GPIO_11
D10
GPIO_7
D8
GPIO_5
D12
REXT
C14
LVB1M
C13
LVB1P
A13
LVB0M
B13
LVB0P
D7
GPIO_4
D9
GPIO_6
B12
LVA4M
A12
LVA4P
C12
LVA3M
C11
LVA3P
A11
LVACKM
B11
LVACKP
B10
LVA2M
A10
LVA2P
C10
LVA1M
C9
LVA1P
A9
LVA0M
B9
LVA0P
F10
AVDD_PLL
G8
GND_2
D11
GPIO_8
D13
GPIO_9
E11
GPIO_12
N7
GPIO[25]
D6
SCLM
D5
SDAM
A14
GPIO_1
B14
GPIO_2
D3
XIN
D4
XOUT
K16
GPIO_14
K15
GPIO_13
H7
GND_5
G11
AVDD_LVDS_2
B8
RO0N
A8
RO0P
C8
RO1N
C7
RO1P
A7
RO2N
B7
RO2P
B6
ROCKN
A6
ROCKP
C6
RO3N
C5
RO3P
A5
RO4N
B5
RO4P
H8
GND_6
F11
AVDD_LVDS_1
B4
RE0N
A4
RE0P
C4
RE1N
C3
RE1P
A3
RE2N
B3
RE2P
B2
RECKN
A2
RECKP
C2
RE3N
C1
RE3P
A1
RE4N
B1
RE4P
GND_9
J7
GND_15K9
LVDS_SEL
BIT_SEL
011:AG22
100uF
16V
C951
20pF
C900
20pF
C902
MDS62110201
M2
MDS62110201
M4
OPT
MDS62110201
M5
MDS62110201
M6
MDS62110201
M7
URSA_B2P
URSA_B2M
URSA_BCKP
URSA_BCKM
URSA_B3P
URSA_B3M
URSA_B4P
URSA_B4M
URSA_C0P
URSA_C0M
URSA_C1P
URSA_C1M
URSA_C2P
URSA_C2M
URSA_D1M
URSA_D1P
URSA_D0M
URSA_D0P
URSA_C4M
URSA_C4P
URSA_C3M
URSA_C3P
URSA_CCKM
URSA_CCKP
URSA_D2P
URSA_D2M
URSA_DCKP
URSA_DCKM
URSA_D3P
URSA_D3M
URSA_D4P
URSA_D4M
URSA_A0P
URSA_A0M
URSA_A1P
URSA_A1M
URSA_A2P
URSA_A2M
URSA_ACKP
URSA_ACKM
URSA_A3P
URSA_A3M
URSA_A4P
URSA_A4M
URSA_B0P
URSA_B0M
URSA_B1P
URSA_B1M
URSA_A[0]
URSA_A[2]
URSA_A[4]
URSA_A[6]
URSA_A[8]
URSA_A[11]
URSA_A[1]
URSA_A[10]
URSA_A[5]
URSA_A[9]
URSA_A[12]
URSA_A[7]
URSA_A[3]
URSA_DQ[0-31]
URSA_DQ[20]
URSA_DQ[19]
URSA_DQ[17]
URSA_DQ[22]
URSA_DQ[27]
URSA_DQ[28]
URSA_DQ[25]
URSA_DQ[30]
URSA_DQ[31]
URSA_DQ[24]
URSA_DQ[26]
URSA_DQ[29]
URSA_DQ[23]
URSA_DQ[16]
URSA_DQ[18]
URSA_DQ[21]
URSA_DQ[4]
URSA_DQ[3]
URSA_DQ[1]
URSA_DQ[6]
URSA_DQ[11]
URSA_DQ[12]
URSA_DQ[9]
URSA_DQ[14]
URSA_DQ[15]
URSA_DQ[8]
URSA_DQ[10]
URSA_DQ[13]
URSA_DQ[7]
URSA_DQ[0]
URSA_DQ[2]
URSA_DQ[5]
URSA_B4M
URSA_B4P
URSA_B3M
URSA_B3P
URSA_B4P
URSA_B3M
URSA_B3P
URSA_BCKM
URSA_BCKP
URSA_BCKP
URSA_B2M
URSA_B2P
URSA_B1M
URSA_B1P
URSA_B0M
URSA_B0P
URSA_B2P
URSA_B1M
URSA_B1P
URSA_B0M
URSA_B0P
URSA_A4M
URSA_A4P
URSA_A3M
URSA_A3P
URSA_A4P
URSA_A3M
URSA_A3P
URSA_ACKM
URSA_ACKP
URSA_ACKP
URSA_A2M
URSA_A2P
URSA_A1M
URSA_A1P
URSA_A0M
URSA_A0P
URSA_A2P
URSA_A1M
URSA_A1P
URSA_A0M
URSA_A0P
URSA_D4M
URSA_D4P
URSA_D3M
URSA_D3P
URSA_D4P
URSA_D3M
URSA_D3P
URSA_DCKM
URSA_DCKP
URSA_DCKP
URSA_D2M
URSA_D2P
URSA_D1M
URSA_D1P
URSA_D0M
URSA_D0P
URSA_D2P
URSA_D1M
URSA_D1P
URSA_D0M
URSA_D0P
URSA_C4M
URSA_C4P
URSA_C3M
URSA_C3P
URSA_C4P
URSA_C3M
URSA_C3P
URSA_C0P
URSA_C0M
URSA_CCKM
URSA_CCKP
URSA_CCKP
URSA_C2M
URSA_C2P
URSA_C1M
URSA_C1P
URSA_C2P
URSA_C1M
URSA_C1P
SPI FLASH
XTAL
FRC
12
9
EAX60890801
GPIO8
HIGH
HIGH
I2C
EEPROM
S P I
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
PWM1
PWM0
Placed on SMD-TOP
Placed on SMD-TOP
GPIO12
LOW
GPIO14
VENUS (MST7329N)
HIGH
URSAII MINI LVDS TYPE
LOW
URSAII LVDS TYPE
LOW
M+S NORMAL 42"(MST7327N)
LOW
HIGH
URSAII MINI LVDS TYPE
I S P P o r t f o r F R C
HIGH
HIGH
URSAII MINI LVDS TYPE
M+S GIP 37"(MST7327N)
M+S NORMAL 47"(MST7327N)
2 0 0 9 . 0 4 . 1 6
CONTACT TO MODULE FOR EMI
L : 8 b i t
V4 LGD BIT SEL
H o r N C : 1 0 b i t
V4 LGD OPC
V4 LGD LVDS SEL
H : ENABLE
H : J E I D A
L or NC : DISABLE
L o r N C : V E S A
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
56
AR1000
56
AR1002
56
AR1001
56
AR1003
22
AR1013
22
AR1014
22
AR1015
URSA_DQ[0-31]
011:AA4;012:AL20
150
R1000
OPT
56
AR1006
56
AR1005
56
AR1007
22
AR1010
56
AR1004
22
AR1011
22
AR1012
150
R1039
OPT
URSA_DQ[0-31]
011:AA4;012:E20
URSA_A[0-12]
+1.8V_FRC_DDR
+1.8V_FRC_DDR
+1.8V_FRC_DDR
+1.8V_FRC_DDR
+1.8V_FRC_DDR
+1.8V_FRC_DDR
+1.8V_FRC_DDR
+1.8V_FRC_DDR
+1.8V_FRC_DDR
+1.8V_FRC_DDR
22
R1025
22
R1027
22
R1008
22
R1024
22
R1005
22
R1006
56
R1033
56
R1034
56
R1032
56
R1014
56
R1031
56
R1015
56
R1012
56
R1035
56
R1016
56
R1036
56
R1017
56
R1013
10uF
C1023
10uF
C1028
10uF
C1002
22
AR1016
22
AR1017
URSA_MCLKZ
011:H10
URSA_BA1
0 1 1 : Q 4 ; 0 1 2 : T 9
URSA_WEZ
0 1 1 : Q 4 ; 0 1 2 : T 8
URSA_RASZ
URSA_DQM3
011:H15
URSA_MCLKE
0 1 1 : S 4 ; 0 1 2 : T 9
URSA_DQSB3
011:H13
URSA_ODT
0 1 1 : H 1 0 ; 0 1 2 : Y 1 4
URSA_CASZ
URSA_DQM2
011:H15
B_URSA_BA0
URSA_BA0
0 1 1 : Q 4 ; 0 1 2 : T 9
URSA_DQS2
011:H14
B_URSA_BA1
URSA_MCLK
011:H11
URSA_DQS3
011:H13
URSA_DQSB2
011:H14
B_URSA_MCLKE
0 1 2 : T 1 0
B_URSA_WEZ
0 1 2 : T 1 0
B_URSA_BA1
B_URSA_BA0
B_URSA_WEZ
012:Q13
B_URSA_MCLKE
012:Q14
B_URSA_RASZ
012:R16
B_URSA_CASZ
012:R16
B_URSA_RASZ
B_URSA_CASZ
22
AR1018
22
AR1019
A_URSA_BA1
012:AA15
A_URSA_BA0
012:AA15
A_URSA_MCLKE
0 1 2 : Z 1 4
A_URSA_WEZ
012:Y13
URSA_BA0
0 1 1 : Q 4 ; 0 1 2 : V 1 0
URSA_BA1
0 1 1 : Q 4 ; 0 1 2 : V 1 0
URSA_WEZ
0 1 1 : Q 4 ; 0 1 2 : V 1 0
URSA_MCLKE
0 1 1 : S 4 ; 0 1 2 : V 1 0
A_URSA_RASZ
A_URSA_CASZ
URSA_RASZ
URSA_CASZ
A_URSA_MCLKE
012:V9
URSA_MCLKZ1
011:AA4
URSA_DQS0
011:W4
A_URSA_CASZ
012:X16
URSA_DQSB0
011:W4
URSA_DQM1
011:V4
A_URSA_BA1
A_URSA_BA0
A_URSA_RASZ
012:X16
URSA_MCLK1
0 1 1 : Z 4
A_URSA_WEZ
012:V8
URSA_ODT
0 1 1 : H 1 0 ; 0 1 2 : Q 1 4
URSA_DQS1
011:X4
URSA_DQM0
011:V4
URSA_DQSB1
011:X4
10uF
1
0
V
C1001
10uF
1
0
V
C1022
1K
1
%
R1002
1K
1
%
R1038
1K
1
%
R1001
1K
1
%
R1037
0.1uF
C1020
0.1uF
C1016
0.1uF
C1007
0.1uF
C1015
0.1uF
C1009
0.1uF
C1018
0.1uF
C1004
0.1uF
C1025
0.1uF
C1026
0.1uF
C1012
0.1uF
C1027
0.1uF
C1005
0.1uF
C1019
0.1uF
C1011
0.1uF
C1003
0.1uF
C1006
0.1uF
C1017
0.1uF
C1024
0.1uF
C1014
0.1uF
C1013
0.1uF
C1039
0.1uF
C1038
0.1uF
C1029
0.1uF
C1041
0.1uF
C1037
0.1uF
C1031
0.1uF
C1040
0.1uF
C1034
0.1uF
C1033
0.1uF
C1036
0.1uF
C1035
0.1uF
C1030
0.1uF
C1010
H5PS5162FFR-S6C
IC1000
J 2
VREF
J 8
CK
H2
VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
NC4
L2
BA0
R8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC5
L3
BA1
J 7
VSSDL
L7
CAS
F2
VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC6
M7
A2
N7
A6
M8
A0
J 1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8
VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J 3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J 9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
H5PS5162FFR-S6C
IC1001
J 2
VREF
J 8
CK
H2
VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
NC4
L2
BA0
R8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC5
L3
BA1
J 7
VSSDL
L7
CAS
F2
VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC6
M7
A2
N7
A6
M8
A0
J 1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8
VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J 3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J 9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
DDR_DQ[16-31]
DDR_DQ[16]
DDR_DQ[17]
DDR_DQ[18]
DDR_DQ[19]
DDR_DQ[20]
DDR_DQ[21]
DDR_DQ[22]
DDR_DQ[23]
DDR_DQ[24]
DDR_DQ[25]
DDR_DQ[26]
DDR_DQ[27]
DDR_DQ[28]
DDR_DQ[29]
DDR_DQ[30]
DDR_DQ[31]
DDR_DQ[27]
DDR_DQ[28]
DDR_DQ[25]
DDR_DQ[30]
DDR_DQ[22]
DDR_DQ[17]
DDR_DQ[19]
DDR_DQ[20]
DDR_DQ[31]
DDR_DQ[24]
DDR_DQ[26]
DDR_DQ[29]
DDR_DQ[23]
DDR_DQ[16]
DDR_DQ[18]
DDR_DQ[21]
DDRB_A[0-12]
DDRB_A[0]
DDRB_A[1]
DDRB_A[2]
DDRB_A[3]
DDRB_A[4]
DDRB_A[5]
DDRB_A[6]
DDRB_A[7]
DDRB_A[8]
DDRB_A[9]
DDRB_A[10]
DDRB_A[11]
DDRB_A[12]
DDRB_A[10]
DDRB_A[1]
DDRB_A[9]
DDRB_A[12]
DDRB_A[7]
DDRB_A[5]
DDRB_A[0]
DDRB_A[2]
DDRB_A[4]
DDRB_A[6]
URSA_DQ[27]
URSA_DQ[28]
URSA_DQ[25]
URSA_DQ[30]
URSA_DQ[22]
URSA_DQ[17]
URSA_DQ[19]
URSA_DQ[20]
URSA_DQ[31]
URSA_DQ[24]
URSA_DQ[26]
URSA_DQ[29]
URSA_DQ[23]
URSA_DQ[16]
URSA_DQ[18]
URSA_DQ[21]
URSA_A[10]
URSA_A[1]
URSA_A[9]
URSA_A[12]
URSA_A[7]
URSA_A[5]
URSA_A[0]
URSA_A[2]
URSA_A[4]
URSA_A[6]
DDRA_A[2]
URSA_DQ[4]
DDR_DQ[11]
DDRA_A[1]
URSA_DQ[6]
DDR_DQ[10]
DDRA_A[0]
DDR_DQ[9]
DDR_DQ[8]
DDR_DQ[7]
URSA_DQ[14]
URSA_DQ[2]
DDR_DQ[6]
URSA_DQ[9]
DDR_DQ[5]
URSA_DQ[0]
DDR_DQ[4]
URSA_DQ[7]
DDRA_A[0-12]
DDRA_A[4]
DDR_DQ[3]
DDR_DQ[4]
DDRA_A[6]
DDR_DQ[2]
URSA_DQ[12]
URSA_DQ[11]
DDR_DQ[3]
DDRA_A[0]
DDR_DQ[1]
DDRA_A[2]
DDR_DQ[1]
DDR_DQ[0]
DDRA_A[5]
DDR_DQ[6]
DDRA_A[7]
DDR_DQ[14]
URSA_DQ[5]
URSA_DQ[15]
DDRA_A[12]
DDR_DQ[9]
DDRA_A[9]
DDR_DQ[12]
DDR_DQ[11]
DDRA_A[10]
DDR_DQ[5]
DDRA_A[1]
DDR_DQ[2]
DDR_DQ[0]
DDRA_A[12]
DDR_DQ[0-15]
URSA_DQ[3]
DDR_DQ[7]
DDRA_A[11]
DDR_DQ[13]
DDRA_A[10]
URSA_DQ[10]
DDR_DQ[10]
DDRA_A[9]
URSA_DQ[8]
DDR_DQ[8]
DDRA_A[8]
DDR_DQ[15]
DDRA_A[7]
DDR_DQ[15]
DDRA_A[6]
URSA_DQ[13]
DDRA_A[5]
DDR_DQ[14]
DDRA_A[4]
DDR_DQ[13]
DDRA_A[3]
URSA_DQ[1]
DDR_DQ[12]
DDRA_A[3]
URSA_A[3]
URSA_A[1]
URSA_A[10]
URSA_A[9]
URSA_A[12]
URSA_A[7]
URSA_A[5]
URSA_A[2]
URSA_A[0]
URSA_A[6]
URSA_A[4]
DDRB_A[11]
DDRB_A[8]
DDRA_A[8]
DDRA_A[11]
URSA_A[11]
URSA_A[8]
URSA_A[8]
URSA_A[11]
URSA_A[3]
DDRB_A[3]
DDR2 1.8V By CAP - Place these Caps near Memory
FRC DDR2
10
12
EAX60890801
2 0 0 9 . 0 4 . 1 6