LG 42LX6500-SD (CHASSIS:LJ03R) Service Manual ▷ View online
0
GP2-BCM (Brazil) trouble shooting guide
1
D-sub RGB
HDMI 1
NAND Flash
(8G bit)
Digital Audio (Optic)
USB /DVR Ready
Digital AMP
NTP7000
RS-232C (Ctrl./SVC)
4x1
HDMI Switch
TDA19997
I2C_2
I2S
NVRAM
I2C_3
RGB/H/V
DDR_D0[0:15], DQS, DM …
Addr.[ 0:13], ctrl. data
MAX3232
BCM3556P
BCM3556P
(ISDB
(ISDB
-
-
T)
T)
Data [0 … 7]
SIF
CVBS
REAR AV
Component 1
Y Pb Pr, L/R
CVBS, L/R
HDMI4
Component 2
Y Pb Pr, L/R
Audio L/R
Audio L/R (for RGB)
HDMI 2
HDMI 3
SPDIF
DP/DM/ +5V
RX/TX
JACK PACK
JACK PACK
at RE
A
R
at RE
A
R
JACK PACK
JACK PAC
K
at SIDE
at SIDE
SCL, SDA_3.3V
Main tuner
(TDTR-T055F)
IF +/-
IF_AGC
De-mode
MN88443
FE_TS_VAL_ERR
RF-module
8Bit MCU
(CC2510)
IR module
IR
UART
RF
IR
IR+RF Board
RF Remocon
Ethernet Connect
DDR2 (1Gbit)
IC603
DDR2 (1Gbit)
IC604
DDR2 (1Gbit)
IC605
DDR2 (1Gbit)
IC606
DDR_D1[0:15], DQS, DM …
X-tal
54MHz
HP L/R out
LG5111
Local
dimming
I2C_3
LVDS
60Hz
IIC
LVDS
60Hz
USB
Wireless module
I2C_3
UART
MICOM
(uPD78F0513)
I2C_1
SCL, SDA_3.3V
Block Diagram
LGE Confidential
X-tal
32.768KHz
Main B/D
IIC
Digital AMP
NTP7000
Digital AMP
NTP7000
SIDE_CVBS Phone JACK
CVBS, L/R
SIDE_Component Phone
Jack
Y Pb Pr
3D_Glasses_Sync
3D_L/R_Sync
FRC
(LGE1120)
X-tal
25MHz
EEPROM
EEPROM
EEPROM
DDR2
512MBIT
ALTERA
(EP3C55)
X-tal
54MHz
EEPROM
DDR2
512MBIT
LVDS
240Hz
TL2425
TL2425
Formatter B/D
IR Emitter for shutter glasses
FE_TS_SYNC
FE_TS_SERIAL
FE_TS_DATA_CLK
FE_TS_DATA_CLK
2
2. 3D Formatter B/D
LG1120 (FRC)
S-Flash
(2MBIT)
DDR2 * 4
(512MBIT)
HW option
Dual Display
Control with
240Hz
(FRC)
TL2425MC(T-CON)
TL2425MC(T-CON)
LVDS_TX4(DATA[10]+CLK[2]
LVDS_TX3(DATA[10]+CLK[2]
LVDS_TX2(DATA[10]+CLK[2]
LVDS_TX1(DATA[10]+CLK[2]
LVDS_TX8(DATA[10]+CLK[2]
LVDS_TX7(DATA[10]+CLK[2]
LVDS_TX6(DATA[10]+CLK[2]
LVDS_TX5(DATA[10]+CLK[2]
(960 X 1080 @ 240Hz)
(960 X 1080 @ 240Hz)
EEPROM
EEPROM
To panel
Left mini-LVDS signals (data[12]+clk[2]
Right mini-LVDS signals (data[12]+clk[2]
Left mini-LVDS signals (data[12]+clk[2]
Right mini-LVDS signals (data[12]+clk[2]
(960 X 1080 @ 240Hz)
(960 X 1080 @ 240Hz)
FPGA
(EP3C55F484C6N)
DDR2 * 2
(512MBIT)
S-Flash
EPCS16SI8N
(2MBIT)
LVDS_TX4(DATA[10]+CLK[2]
LVDS_TX3(DATA[10]+CLK[2]
LVDS_TX2(DATA[10]+CLK[2]
LVDS_TX1(DATA[10]+CLK[2]
LVDS_TX8(DATA[10]+CLK[2]
LVDS_TX7(DATA[10]+CLK[2]
LVDS_TX6(DATA[10]+CLK[2]
LVDS_TX5(DATA[10]+CLK[2]
(960 X 1080 @ 240Hz)
(960 X 1080 @ 240Hz)
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