LG 32PG6000-ZA (CHASSIS:PD81A) Service Manual ▷ View online
- 21 -
BLOCK DIAGRAM
Main Block Diagram
COMP1
RGB
HDMI1,
HDMI2,
HDMI3
SCART1
Side AV1
TS[0:7]
CVBS, Y/C, L/R
SCART2
DDR2 SDRAM
(64MByte)
Qimonda
IC701
NOR Flash
(32MB)
SPANSION
IC404
WXGA
Panel
SPDIF
USB
SPDIF_OUT
Digital amp
(NTP3000A)
IC601
RS-232C
TMDS351PAG
IC201
Y
Pb
Pr, L/R
RGB, CVBS, audio L/R
CVBS
DTV/MNT OUT
I2S
EEPROM
24LC512
IC907
HDMI4
RGB, L/R
Tuner
(TDFV-G135D1)
TU301
TMDS[0:7]
74LVC541A(PW)
Buffer
IC402
PCMCIA
Card
74LVC542A5
Bi-Buffer
IC405
DATA[0:7]
74LCX244MTC
Buffer
IC406,407,408
Address[0:14]
TMDS[0:7]
CVBS, SIF, AM Audio
Tuner V out
NLASB3157
IC502
LVDS TMDS ODD[10 bit]
Host Address[1:16]
Host Data[0:15]
LPF
DDR2 Data[0:15]
DDR2 SDRAM
(64MByte)
Qimonda
IC701
DDR2 Data[16:31]
DDR2 Address[0:12]
I2C
MICOM
WT61P8
IC802
I2C
MAX3232CDR
IC101
TX/RX
TX
NLASB3157
IC1013
TX
TX
AT24C16AN
IC801
FLI10306
TS[0], CLK, SY, VAL
Module I2C
RX
Audio L/R out
Audio L/R out
MSP4458
Audio L/R in
Audio L/R in
I2S
Muxed
audio
L/R Audio
Only
Demux
Only for DTV
Audio
MPE
- 22 -
MI
C
O
M
Le
v
e
l
ge
n
e
ra
to
r
0V
,6
V
,11V
1
2
V-
>
3
.3
V
L
ev
el
s
h
if
te
r
RE
C
8
C
tr
l1
RE
C
8
C
tr
l2
D
T
V/
M
N
T
_VO
U
T
Sc
a
rt
2
I
D
Re
c
o
rd
in
gC
tr
l
Sc
a
rt
1
F
B
Sc
a
rt
1
C
V
B
S
T
U
N
E
R_
VO
U
T
N
L
A
S
B
3157
Vi
d
e
o
S
/W
TR
B
U
F
Sc
a
rt
1
R
,G
,B
1
2
V-
>
3
.3
V
L
ev
el
s
h
if
te
r
Sc
a
rt
1
I
D
SI
D
E
Y
/C
V
B
S
SI
D
E
C
SI
D
E
R
SI
D
E
L
S
ID
ESS
/W
Sc
a
rt
1
L
/R
TV
O
U
T
L
/R
Le
v
e
lA
d
j
[
L
B
A
D
C
_I
N
4
]
[A
2
P
],
[B
2
P
],
[C
2
P
]
[A
4
P
]
[C
4
P
]
[S
C
A
R
T
_F
B
]
TR
A
d
j
[
15]
V
ID
E
O
[A
U
D
_I
N
_I
2
S
]
TR
B
U
F
TR
N
e
t
[
G
P
IOA
4
]
M
U
T
E
_L
IN
E
TR
A
d
j
[S
V
3
P
]
T
U
_M
A
IN
LP
F
Le
v
e
lA
d
j
Sc
a
rt
1
L
in
k
VX
O
_
D
E
Sc
a
rt
2
C
V
B
S
[S
V
4
P
]
[
V
X
I_
D
15]
[
V
X
I_D
1
6
]
Sc
a
rt
2
I
D
[L
B
A
D
C
_I
N
5
]
[V
D
A
C
_G
Y
_Y
C
_P
]
[V
O
U
T
2
]
TR
A
M
P
[
6
d
B
]
[V
X
O
_D
1
3
]
D
T
V/
M
N
T
s
w
it
c
hC
tr
l
Le
v
e
lA
d
j
Sc
a
rt
2
L
in
k
VX
O
_VS
Sc
a
rt
2
L
/R
Le
v
e
lA
d
j
[A
UD
_O
UT
1
_L
,R
]
TR
B
U
F
[
G
P
IOA
5
]
M
U
T
E
_L
IN
E
_
D
T
V
D
T
V/
M
N
TL
/R
LP
F
LP
F
Le
v
e
lA
d
j
Le
v
e
lA
d
j
[S
V
2
P
]
[B
4
P
]
[A
U
D
_I
N
_R
4
]
[A
U
D
_I
N
_L
4]
[V
X
O
_D
11]
SI
D
E
C
V
B
S
L
in
k
[V
X
O
_
D
1
]
F
LI
10306
MI
C
O
M
TU
N
E
R
TR
N
e
t
M
S
P
4458
M
S
P
4458
SI
F
AM
A
U
D
IO
I2
S
Mu
x
e
d
A
u
d
io
Mu
x
e
d
A
u
d
io
[A
UD
_O
UT
1
_L
,R
]
TR
A
d
j
1:Audio R out (TV)
2:audio R in
3:audio L out (TV)
4:audio GND
5:blue GND
6:audio L in
7:Blue
8:SCART ID
9:green GND
10:data 2 (NC)
11:Green
12:data1 (NC)
13: Link (red GND)
14:data GND (NC)
15:Red
16:SCART FB
17:video GND
18:RGB Control GND
19:CVBS out (TV out)
20:CVBS in
21:safety GND
22:GND
23:GND
1:Audio R out (DTV)
2:audio R in
3:audio L out (DTV)
4:audio GND
5:GND
6:audio L in
7:NC
8:function select
9: NC
10:data 2 (NC)
11:NC
12:data1 (NC)
13: Link
14:data GND (NC)
15: NC
16: NC
17:video GND
18:GND
19:CVBS out (DTV out)
20:CVBS in
21:safety GND
22:GND
23:GND
SCART 1
SCART 2
- 23 -
BlockDiagram
( Component & RGB & HDMI)
COMP_Y
COMP_PB
COMP_PR
VGA_R
VGA_B
VGA_G
HSYNC
VSYNC
EDID
EEPROM
AT24C02BN
D_SUB_I2C
COMP_L
COMP_R
PC L,R
[A3P]
[B3P]
[C3P]
[VXO_D0]
[AUD_IN_L3]
[AVS]
[AHS_ACS]
[A1P]
Level Adj
Level Adj
[AUD_IN_R3]
COMP Link
[B1P]
[C1P]
74HC14D
Schmitt triggering
Usage : BUF
[VXO_HS]
RGB Link
[AUD_IN_L5,R5]
HDMI 2 TMDS[8bit]
DDC HDMI2 I2C
EDID
AT24C02BN
HDMI 3 TMDS[8bit]
DDC HDMI3 I2C
EDID
AT24C02BN
HDMI SW TMDS[8bit]
HDMI I2C [SW]
HDMI EQ Ctrl
[VXO_D6]
[GPIOA0]
[GPIOA1]
HDMI Select 1
HDMI Select 2
CEC_REMOTE
[GPIOB1]
[2WIRE_S1]
[2WIRE_S0]
[DSDA1,DSCL1]
HDMI SW TMDS[8bit]
DDC HDMI4 I2C
EDID
AT24C02BN
[2WIRE_S2]
[BRX]
[ARX]
[VXO_D20]
[VXO_D21]
HDMI1 5V DET
HDMI3 5V DET
HDMI4 5V DET
[VXO_CLK]
HP DET S/W4
[VXI_D23]
HP DET S/W1
HP DET S/W3
[HDMI_B_HPD]
[HDMI_A_HPD]
[VXO_D22]
FET Bi-BUF
NLASB3157
IC502
2 RX
CHAPLIN RX
UCOM RX
3 TX
UCOM TX
CHAPLIN TX
6 RX
4TX
G-probe
FLI10306
MICOM
MICOM
TMDS351PAG
IC201
MAX3232CDR
IC101
HDMI 2 TMDS[8bit]
DDC HDMI2 I2C
EDID
AT24C02BN
HDMI2 5V DET
HP DET S/W2
[VXO_D19]
- 24 -
BlockDiagram
( FE & PCMCIA)
CI_TS[0:7]
Tuner
(TDFV-G135D1)
TU301
74LVC541A(PW)
Buffer
IC402
PCMCIA
Card
74LVC542A5
Bi-Buffer
IC405
HOST DATA[0:7]
FE_TS[0:7]
FLI10306
HOST Address[1:24]
HOST DATA[0:15]
FLASH WP Ctrl
[OOB_CTX]
RESET
[GPIOE7]
HOST Write Enable
[POD_WE_HOST_WR]
HOST Out Enable
[POD_OE_HOST_RD]
HOST Chip Enable
[HOST_BOOD_CS_N]
CI DATA[0:7]
[POD_DIR_N]
CI DATA Dir Select
CI Detect
[POD_DETECT_N]
CI Detect
TS_IN[0:7]
74LCX244MTC
Buffer
IC406
HOST Address[0:3]
POD Address[4:7]
CI Address[0:7]
74LCX244MTC
Buffer
IC407
HOST Address[10:13]
POD Address[8;9;14]
HOST Address[4]
74LCX244MTC
Buffer
IC408
REG
CI Detect
CI Detect
CI Address[8:14]
CI Detect
[POD_OE_HOST_RD]
HOST Out Enable
CI Out Enable
HOST Write Enable
CI Write Enable
HOST Address[6]
CI IORD
HOST Address[5]
CI IOWR
FE_TS_DATA_VAL
CI_MIVAL
FE_TS_DATA_SYN
CI_MISTRT
FE_TS_DATA_CLK
CI_MICLK
Tuner
(TDFV-G135D1)
TU301
TPS2042BDRG4
Power
Distributer
IC301
5V
600mA
5V
5V_ANN_MNT
5V_ANN_CTL
[AUDO_I2SB_DAT1]
[AUDO_I2SB_DAT2]
S29GL256N10TFI020
NOR Flash
FLI10306
MICOM
TS[0], CLK, SY, VAL
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