LG 32LH40 / 32LH41 (CHASSIS:LA92B) Service Manual ▷ View online
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
URSA_RASZ
M E
M C
_ R
X O
0 -
001:R36
+3.3V_MEMC
+3.3V_MEMC
100
R812
URSA_DQS3
009:Q13
0
R843
OPC_EN
M E
M C
_ R
X E
4 +
001:R38
0.
1u
F
C829
URSA_CASZ
M E
M C
_ R
X E
2 -
001:R38
M_SPI_CK
URSA_DQSB3
009:Q12
M E
M C
_ R
X O
0 +
001:R36
U R
S A
_ W
E Z
M E
M C
_ R
X E
3 -
001:R38
1000pF
C849
URSA_MCLK
009:Q16
0.1uF
C828
0.1uF
C822
0.1uF
C820
OPC_EN
M E
M C
_ R
X O
2 -
001:R35
MEMC_RESET
001:AB21
0
OPC_EN
R842
1K
R809
OPT
2.2K
R190
0.1uF
C834
BLM18PG121SN1D
L806
100
R821
0.1uF
C832
+3.3V_MEMC
BLM18PG121SN1D
L800
1uF
C805
URSA_BA1
2.2K
R204
M_SPI_DI
0
OPT
R845
+3.3V_ST
0
OPT
R854
0
R
846
M E
M C
_ R
X O
1 -
001:R36
URSA_BA0
M_SPI_DO
0.
1u
F
C850
OPT
10uF
10V
C815
10uF
C816
1K
R808
100
R823
U R
S A
_ M
C LK
E
M_SPI_CZ
22uF
16V
C811
1K
R827
OPT
MEMC_SCL
001:AI7
10uF
10V
C858
100
R837
0.1uF
C841
10uF
10
V
C807
M E
M C
_ R
X O
2 +
001:R36
1K
R851
0.
1u
F
C836
1KOPT
R850
+5V_GENERAL
URSA_A[0-12]
BLM18PG121SN1D
L805
M E
M C
_ R
X O
4 +
001:R35
0
R835
M E
M C
_ R
X O
3 -
001:R35
0.1uF
C831
1K
R828
PWM_DIM
M_XTALI
008:P27
0.1uF
C825
1uF
C823
M E
M C
_ R
X E
0 -
001:R39
0.1uF
C824
M_SPI_CZ
008:Y11
0.
1u
F
C837
M E
M C
_ R
X O
3 +
001:R35
10K
R811
M_SPI_DO
008:Y11
BIT_SEL
M E
M C
_ R
X O
C -
001:R34
22uF
25V
C848
ISP_TXD_TR
008:C23
0.1uF
C847
URSA_MCLKZ
009:Q15
URSA_DQSB0
0.
1u
F
C814
100
R814
0.1uF
C845
U R
S A
_ M
C LK
1
0.1uF
16V
C856
M E
M C
_ R
X O
C +
001:R34
M E
M C
_ R
X E
C +
001:R37
10uF
10V
C804
URSA_ODT
009:Q15;009:Y15
URSA_DQS1
1KOPT
R848
U R
S A
_ M
C L
K Z
1
M E
M C
_ R
X E
3 +
001:R38
URSA_DQ[0-31]
009:D21;009:AL21
URSA_DQSB1
0.
1u
F
C830
OPC_OUT1
+3.3V_MEMC
URSA_DQM3
009:Q13
BLM18PG121SN1D
L804
0.1uF
C819
0.
1u
F
C817
0.
1u
F
C827
LVDS_SEL
100
R815
100
R819
+1.8V_MEMC
M_SPI_CK
008:Y10
M_SPI_DI
008:Y11
SMW250-04
P101
URSA_Debug
1
2
3
4
0.
1u
F
C851
12MHz
X800
56
R806
0
R824
0.1uF
C
8
2
1
100
R813
1K
R826
1M
R804
10K
R803
100
R822
10uF
C809
100
R818
56
R802
0.
1u
F
C838
M E
M C
_ R
X E
0 +
001:R39
56
R801
10uF
C812
0.
1u
F
C803
0.1uF
C846
U R
S A
_ D
Q M
1
100
R820
0.
1u
F
C852
10K
R810
0.1uF
C818
0.
1u
F
C839
100
R838
56
R807
+3.3V_MEMC
0
R836
0.1uF
C826
0.1uF
C844
15pF
C801
10uF
C813
M E
M C
_ R
X E
C -
001:R37
+3.3V_MEMC
ISP_RXD_TR
008:C23
1K
R849
U R
S A
_ D
Q M
0
LVDS_SEL
ISP_RXD_TR
001:L5
100
R817
+1.26V_MEMC
M E
M C
_ R
X E
4 -
001:R37
URSA_DQS0
100
R816
M E
M C
_ R
X E
1 +
001:R39
+3.3V_MEMC
M E
M C
_ R
X O
4 -
001:R35
15pF
C800
0
OPT
R833
0
OPC_EN
R847
10uF
C810
M_XTALO
008:P27
0
R2219
OPT
0.
1u
F
C854
0.1uF
C833
OPC_OUT2
M _X
T A
L O
008:AF11
+3.3V_MEMC
+3.3V_MEMC
BLM18PG121SN1D
L803
URSA_DQM2
009:Q13
0.
1u
F
C842
1K
R829
OPT
BLM18PG121SN1D
L801
M_XTALI
00
8:
AJ
11
0.1uF
C835
CB3216PA501E
L807
URSA_DQS2
009:Q13
M E
M C
_ R
X E
2 +
001:R38
W25X20AVSNIG
IC800
3
WP
2
DO
4
GND
1
CS
5
DIO
6
CLK
7
HOLD
8
VCC
ISP_TXD_TR
001:L5
MEMC_SDA
001:AI7
0.1uF
16V
C857
0.1uF
C840
BLM18PG121SN1D
L802
URSA_DQSB2
009:Q12
0.
1u
F
C802
10uF
C806
12V_TCON
0.
1u
F
C855
0.
1u
F
C853
22uF
16V
C808
10K
R831
M E
M C
_ R
X E
1 -
001:R39
0.
1u
F
C843
820
R825
M E
M C
_ R
X O
1 +
001:R36
[E1]
[D1]
[L9]
[N5]
[N4]
[N12]
[N13]
LGE7329A
IC801
E1
SDAS
D1
SCLS
F1
GPIO[8]
G1
GPIO[9]
K8
GND_14
E5
VDDC_1
E2
GPIO[10]
F2
GPIO[11]
F3
GPIO[12]
G2
GPIO[13]
M4
GPIO[22]
M5
GPIO[23]
G3
GPIO[14]
E4
GPIO[15]
F4
GPIO[16]
G4
GPIO[17]
H4
GPIO[18]
J4
GPIO[19]
K4
GPIO[20]
L4
GPIO[21]
J6
VDDP_2
H9
GND_7
F6
VDDC_2
H1
MDATA[20]
H2
MDATA[19]
H3
MDATA[17]
J1
MDATA[22]
J2
MDATA[27]
J3
MDATA[28]
K1
MDATA[25]
K2
MDATA[30]
K6
AVDD_DDR_2
K3
DQM[3]
L1
DQM[2]
J8
GND_10
L2
DQS[2]
L3
DQSB[2]
L6
AVDD_DDR_4
L8
VDDP_3
H10
GND_8
M1
DQS[3]
M2
DQSB[3]
L7
AVDD_DDR_5
M3
MDATA[31]
N1
MDATA[24]
J9
GND_11
N2
MDATA[26]
N3
MDATA[29]
L10
AVDD_DDR_6
P1
MDATA[23]
R1
MDATA[16]
T1
MDATA[18]
T2
MDATA[21]
R2
MCLK[0]
P2
MCLKZ[0]
G7
GND_1
L9
AVDD_MEMPLL
N5
MVREF
N4
ODT
T3
R A
S Z
R3
C A
S Z
P3
MADR[0]
T4
MADR[2]
R4
MADR[4]
J1
0
GND_12
P4
MADR[6]
T5
MADR[8]
R5
MADR[11]
P5
W E
Z
T6
BADR[1]
R6
BADR[0]
P6
MADR[1]
T7
MADR[10]
L11
A V
D D
_ D
D R
_ 7
R7
MADR[5]
P7
MADR[9]
T8
MADR[12]
R8
MADR[7]
P8
MADR[3]
N8
M C
L K
E
K10
GND_16
F7
V D
D C
_ 3
T9
MDATA[4]
R9
MDATA[3]
K7
GND_13
P9
MDATA[1]
T10
MDATA[6]
K11
A V
D D
_ D
D R
_ 3
R10
MDATA[11]
P10
MDATA[12]
T11
MDATA[9]
R11
MDATA[14]
J1
1
A V
D D
_ D
D R
_ 1
P11
DQM[1]
T12
DQM[0]
R12
DQS[0]
P12
DQSB[0]
H11
VDDP_1
T13
DQS[1]
R13
DQSB[1]
P13
MDATA[15]
T14
MDATA[8]
R14
MDATA[10]
P14
MDATA[13]
T15
MDATA[7]
R15
MDATA[0]
P15
MDATA[2]
T16
MDATA[5]
R16
MCLK[1]
P16
MCLKZ[1]
N9
GPIO[26]
N10
GPIO[27]
N11
GND_17
M11
RESET
G6
V D
D C
_ 4
N12
GPIO[28]
N13
GPIO[29]
N14
GPIO[30]
L13
SCK
M13
SDI
M12
SDO
K13
CSZ
L12
PWM1
K12
PWM0
J13
GPIO[0]
H13
GPIO[1]
G13
GPIO[2]
F13
GPIO[3]
E13
GPIO[4]
F12
GPIO[5]
D14
GPIO[6]
E12
GPIO[7]
N6
GPIO[24]
H6
VDDC_5
N15
LVD4M
N16
LVD4P
M14
LVD3M
M15
LVD3P
F8
AVDD_33_1
M16
LVDCKM
L16
LVDCKP
L15
LVD2M
L14
LVD2P
G9
GND_3
K14
LVD1M
J14
LVD1P
J16
LVD0M
J15
LVD0P
H15
LVC4M
H16
LVC4P
H14
LVC3M
G14
LVC3P
G16
LVCCKM
G15
LVCCKP
F15
LVC2M
F16
LVC2P
F14
LVC1M
E14
LVC1P
E16
LVC0M
E15
LVC0P
G10
GND_4
F9
AVDD_33_2
D16
LVB4M
D15
LVB4P
C16
LVB3M
B16
LVB3P
A16
LVBCKM
A15
LVBCKP
B15
LVB2M
C15
LVB2P
D2
GPIO_3
E3
GPIO_10
E10
GPIO_11
D10
GPIO_7
D8
GPIO_5
D12
R E
X T
C14
L V
B 1M
C13
LVB1P
A13
L V
B 0M
B13
LVB0P
D7
GPIO_4
D9
GPIO_6
B12
L V
A 4M
A12
LVA4P
C12
L V
A 3M
C11
LVA3P
A11
L V
A C
K M
B11
L V
A C
K P
B10
L V
A 2M
A10
LVA2P
C10
L V
A 1M
C9
LVA1P
A9
L V
A 0M
B9
LVA0P
F10
A V
D D
_ P
L L
G8
GND_2
D11
GPIO_8
D13
GPIO_9
E11
GPIO_12
N7
GPIO[25]
D6
S C
L M
D5
S D
A M
A14
GPIO_1
B14
GPIO_2
D3
XIN
D4
X O
U T
K16
GPIO_14
K15
GPIO_13
H7
GND_5
G11
AVDD_LVDS_2
B8
R O
0 N
A8
RO0P
C8
R O
1 N
C7
RO1P
A7
R O
2 N
B7
RO2P
B6
R O
C K
N
A6
R O
C K
P
C6
R O
3 N
C5
RO3P
A5
R O
4 N
B5
RO4P
H8
GND_6
F11
AVDD_LVDS_1
B4
RE0N
A4
RE0P
C4
RE1N
C3
RE1P
A3
RE2N
B3
RE2P
B2
R E
C K
N
A2
R E
C K
P
C2
RE3N
C1
RE3P
A1
RE4N
B1
RE4P
GND_9
J7
GND_15
K9
TF05-51S
P800
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
TF05-41S
P801
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
T-GASKET_10X8
GAS1
SMD_Gasket_1
T-GASKET_10X8
GAS2
SMD_Gasket_2
T-GASKET_10X8
GAS3
SMD_Gasket_3
T-GASKET_10X8
GAS4
SMD_Gasket_4
T-GASKET_10X8
GAS5
SMD_Gasket_5
URSA_DQ[2]
URSA_B+[4]
URSA_DCK-
URSA_C+[4]
URSA_D+[2]
URSA_DQ[17]
URSA_C-[2]
URSA_A+[0]
URSA_DQ[24]
URSA_A+[3]
URSA_A-[4]
URSA_A+[0]
URSA_C-[4]
URSA_B+[0]
URSA_C-[3]
URSA_C+[0]
URSA_A-[1]
URSA_DQ[26]
URSA_A[5]
URSA_DQ[0]
URSA_DQ[0-31]
URSA_A-[2]
URSA_A[1]
URSA_D+[1]
URSA_B+[0]
URSA_D+[0]
URSA_A[10]
URSA_A+[2]
URSA_DQ[9]
URSA_C-[4]
URSA_D-[2]
URSA_A-[3]
URSA_C-[0]
URSA_C+[0]
URSA_B-[1]
URSA_DQ[5]
URSA_DQ[18]
URSA_B+[3]
URSA_DQ[8]
URSA_B-[0]
URSA_B-[1]
URSA_A-[3]
URSA_A+[3]
URSA_DQ[6]
URSA_B-[2]
URSA_A[12]
URSA_A[2]
URSA_CCK+
URSA_CCK+
URSA_DQ[21]
URSA_B-[4]
URSA_DQ[25]
URSA_B+[1]
URSA_C+[2]
URSA_DQ[27]
URSA_DCK+
URSA_DQ[1]
URSA_D+[4]
URSA_A+[1]
U R
S A
_ A
C K
+
URSA_DQ[13]
URSA_DQ[30]
URSA_A[11]
URSA_B+[2]
URSA_DQ[15]
URSA_A-[0]
URSA_BCK-
URSA_A[6]
URSA_B+[1]
URSA_DQ[31]
URSA_BCK+
URSA_DQ[10]
URSA_B-[2]
URSA_DQ[14]
URSA_B+[3]
URSA_DQ[23]
URSA_DQ[28]
URSA_C-[3]
URSA_B-[3]
URSA_D-[3]
URSA_C+[3]
URSA_C+[1]
URSA_D-[1]
URSA_A[9]
URSA_D+[4]
URSA_D-[3]
URSA_C-[1]
URSA_D+[3]
URSA_BCK-
URSA_A-[4]
URSA_C+[2]
URSA_B+[2]
URSA_DQ[12]
URSA_C-[1]
URSA_C-[0]
URSA_B-[3]
URSA_C+[1]
URSA_A+[4]
URSA_D-[0]
URSA_D+[1]
URSA_CCK-
URSA_D-[4]
URSA_A[0]
URSA_A+[1]
URSA_DQ[11]
URSA_A-[1]
URSA_D-[0]
URSA_A[8]
URSA_DQ[7]
URSA_DCK+
URSA_A[7]
URSA_B+[4]
URSA_C-[2]
URSA_D+[2]
URSA_D-[4]
URSA_ACK-
URSA_DQ[3]
URSA_DQ[29]
URSA_D-[2]
URSA_DQ[19]
URSA_D+[0]
URSA_BCK+
URSA_A-[0]
URSA_A+[4]
URSA_D+[3]
URSA_DQ[16]
URSA_DCK-
URSA_A+[2]
URSA_DQ[4]
URSA_C+[3]
URSA_DQ[22]
URSA_A-[2]
URSA_CCK-
URSA_A[3]
URSA_A[4]
URSA_D-[1]
URSA_B-[0]
URSA_ACK+
URSA_ACK-
URSA_DQ[20]
URSA_C+[4]
URSA_B-[4]
GPIO12 GPIO14
Non M+S LVDS LOW LOW
M+S 42" Mini LVDS LOW HIGH
M+S 47" Mini LVDS HIGH LOW
M+S 37" Mini LVDS HIGH HIGH
SPI FLASH
PI Result
PWM1
EEPROM
PWM0
HIGH
SPI
PI Result
HIGH
I
2
C
HIGH
ISP Port for MEMC
HIGH
LOW
HIGH
LOW
HIGH
HIGH
XTAL
GPIO8
SMD Gasket Option
for FRC one-board
C
2009
LVDS/ FRC
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
A_URSA_BA1
009:V10
0.
1u
F
C940
URSA_ODT
008:C10;009:Q15
56
R909
B_URSA_RASZ
009:Q14
HYB18TC256160BF-2.5
IC900
DDR_Qimonda256
J2
VREF
J8
CK
H2
VSSQ_2
B7
UDQS
N8
A4
P8
A8
L1
NC_4
L2
BA0
R8
NC_3
K7
RAS
F8
VSSQ_3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC_5
L3
BA1
J7
VSSDL
L7
CAS
F2
VSSQ_4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC_6
M7
A2
N7
A6
M8
A0
J1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC_1
N2
A3
P2
A7
H8
VSSQ_1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC_2
E7
VSSQ_5
D8
VSSQ_6
D2
VSSQ_7
A7
VSSQ_8
B8
VSSQ_9
B2
VSSQ_10
P9
VSS_1
N1
VSS_2
J3
VSS_3
E3
VSS_4
A3
VSS_5
G9
VDDQ_1
G7
VDDQ_2
G3
VDDQ_3
G1
VDDQ_4
E9
VDDQ_5
C9
VDDQ_6
C7
VDDQ_7
C3
VDDQ_8
C1
VDDQ_9
A9
VDDQ_10
R1
VDD_1
M9
VDD_2
J9
VDD_3
E1
VDD_4
A1
VDD_5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
A_URSA_WEZ
009:V10
URSA_WEZ
008:K4;009:T10
URSA_DQSB1
008:R4
0.
1u
F
C912
0.
1u
F
C941
0.
1u
F
C910
56
R918
56
R906
HYB18TC256160BF-2.5
IC901
DDR_Qimonda256
J2
VREF
J8
CK
H2
VSSQ_2
B7
UDQS
N8
A4
P8
A8
L1
NC_4
L2
BA0
R8
NC_3
K7
RAS
F8
VSSQ_3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC_5
L3
BA1
J7
VSSDL
L7
CAS
F2
VSSQ_4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC_6
M7
A2
N7
A6
M8
A0
J1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC_1
N2
A3
P2
A7
H8
VSSQ_1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC_2
E7
VSSQ_5
D8
VSSQ_6
D2
VSSQ_7
A7
VSSQ_8
B8
VSSQ_9
B2
VSSQ_10
P9
VSS_1
N1
VSS_2
J3
VSS_3
E3
VSS_4
A3
VSS_5
G9
VDDQ_1
G7
VDDQ_2
G3
VDDQ_3
G1
VDDQ_4
E9
VDDQ_5
C9
VDDQ_6
C7
VDDQ_7
C3
VDDQ_8
C1
VDDQ_9
A9
VDDQ_10
R1
VDD_1
M9
VDD_2
J9
VDD_3
E1
VDD_4
A1
VDD_5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
B_URSA_BA0
009:T11
1K1
%
R921
0.
1u
F
C929
URSA_CASZ
008:J4;009:S17
1000pF
C932
URSA_RASZ
008:I4;009:S17
0.
1u
F
C917
URSA_A[0-12]
008:N4
B_URSA_BA0
009:O16
1K
1 %
R902
B_URSA_MCLKE
009:T11
56
R919
A_URSA_BA1
009:AA16
0.
1u
F
C926
B_URSA_MCLKE
009:Q15
A_URSA_BA0
009:V10
56
R916
0.
1u
F
C925
22
AR908
URSA_ODT
008:C10;009:Y15
+1.8V_FRC_DDR
22
AR906
56
R907
URSA_DQ[0-31]
008:U4;009:D21
B_URSA_BA1
009:T11
+1.8V_FRC_DDR
0.
1u
F
C903
22
AR907
22
AR905
56
R910
1K1
%
R922
150
OPT
R923
0.
1u
F
C931
10uF
C928
0.
1u
F
C916
+1.8V_FRC_DDR
56
AR917
0.
1u
F
C914
+1.8V_FRC_DDR
22
AR909
URSA_DQM1
008:P4
0.
1u
F
C924
56
AR915
URSA_BA0
008:L4;009:V11
+1.8V_FRC_DDR
URSA_DQS0
008:Q4
+1.8V_MEMC
URSA_MCLK1
008:U4
URSA_RASZ
008:I4;009:W17
0.
1u
F
C900
56
AR916
22
AR910
URSA_DQS1
008:R4
A_URSA_RASZ
009:Y14
URSA_DQM2
008:C15
A_URSA_CASZ
009:Y14
0.
1u
F
C905
A_URSA_MCLKE
009:Z15
B_URSA_CASZ
009:R17
URSA_BA1
008:K4;009:T10
URSA_DQS3
008:C13
0.
1u
F
C934
10uF
C923
URSA_DQSB2
008:C14
56
R920
0.
1u
F
C911
0.
1u
F
C904
56
R917
0.
1u
F
C921
URSA_WEZ
008:K4;009:V11
1000pF
C908
0.
1u
F
C936
URSA_DQM0
008:Q4
+1.8V_FRC_DDR
56
AR901
22
AR912
URSA_BA1
008:K4;009:V11
0.
1u
F
C918
+1.8V_FRC_DDR
56
AR902
0.
1u
F
C915
150
OPT
R900
A_URSA_BA0
009:AA16
0.
1u
F
C930
0.
1u
F
C935
22
AR913
0.
1u
F
C939
56
AR914
56
AR900
URSA_DQS2
008:C14
10uF
C913
B_URSA_WEZ
009:T11
0.
1u
F
C927
0.
1u
F
C938
56
R911
+1.8V_FRC_DDR
URSA_MCLKZ1
008:U4
22
AR911
URSA_CASZ
008:J4;009:W17
A_URSA_MCLKE
009:V10
URSA_DQSB0
008:Q4
+1.8V_FRC_DDR
URSA_DQ[0-31]
008:U4;009:AL21
10uF
10
V
C901
URSA_MCLK
008:C11
B_URSA_WEZ
009:Q14
B_URSA_BA1
009:O16
10uF
10
V
C922
0.
1u
F
C906
BLM18PG121SN1D
L900
A_URSA_WEZ
009:Y14
56
R908
B_URSA_CASZ
009:Q14
0.
1u
F
C907
0.
1u
F
C920
A_URSA_RASZ
009:X17
0.
1u
F
C909
URSA_MCLKE
008:M4;009:V11
0.
1u
F
C933
56
R915
22
AR904
0.
1u
F
C919
URSA_DQSB3
008:C13
URSA_DQM3
008:C15
URSA_MCLKZ
008:C10
URSA_MCLKE
008:M4;009:T10
56
AR903
10uF
C902
1K1
%
R901
0.
1u
F
C937
A_URSA_CASZ
009:X17
URSA_BA0
008:L4;009:T10
B_URSA_RASZ
009:R17
22
R905
22
R903
22
R914
22
R913
22
R912
22
R904
0.
1u
F
C943
0.
1u
F
C944
0.
1u
F
C942
0.
1u
F
C945
0.
1u
F
C948
+1.8V_MEMC
0.
1u
F
C952
0.
1u
F
C949
0.
1u
F
C950
0.
1u
F
C951
+1.8V_FRC_DDR
0.
1u
F
C947
0.
1u
F
C946
H5PS5162FFR-S6C
DDR_Hynix512
IC900-*1
J2
VREF
J8
CK
H2
VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
NC4
L2
BA0
R8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC5
L3
BA1
J7
VSSDL
L7
CAS
F2
VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC6
M7
A2
N7
A6
M8
A0
J1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8
VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
H5PS5162FFR-S6C
DDR_Hynix512
IC901-*1
J2
VREF
J8
CK
H2
VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
NC4
L2
BA0
R8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC5
L3
BA1
J7
VSSDL
L7
CAS
F2
VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC6
M7
A2
N7
A6
M8
A0
J1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8
VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
HYB18TC512160CF-2.5
DDR_Qimonda512_DieRevision
IC900-*2
J2
VREF
J8
CK
H2
VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
NC4
L2
BA0
R8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC5
L3
BA1
J7
VSSDL
L7
CAS
F2
VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC6
M7
A2
N7
A6
M8
A0
J1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8
VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
HYB18TC512160CF-2.5
DDR_Qimonda512_DieRevision
IC901-*2
J2
VREF
J8
CK
H2
VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
NC4
L2
BA0
R8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC5
L3
BA1
J7
VSSDL
L7
CAS
F2
VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC6
M7
A2
N7
A6
M8
A0
J1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8
VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
DDR_DQ[23]
URSA_DQ[23]
DDR_DQ[19]
DDRB_A[5]
URSA_A[11]
URSA_DQ[8]
DDRA_A[0]
DDR_DQ[1]
URSA_A[1]
DDRA_A[8]
DDRA_A[9]
DDRA_A[2]
DDRA_A[1]
URSA_DQ[7]
DDRB_A[8]
DDR_DQ[4]
DDRB_A[10]
DDRB_A[1]
DDRB_A[5]
URSA_A[0]
DDR_DQ[17]
URSA_A[7]
URSA_A[8]
DDRB_A[10]
DDR_DQ[8]
DDR_DQ[21]
URSA_DQ[5]
DDR_DQ[14]
DDRB_A[0]
DDR_DQ[31]
DDR_DQ[24]
DDR_DQ[3]
URSA_A[5]
DDR_DQ[6]
URSA_A[8]
URSA_A[3]
DDRA_A[11]
DDR_DQ[12]
URSA_DQ[31]
URSA_DQ[3]
DDRB_A[3]
DDR_DQ[27]
URSA_DQ[1]
URSA_DQ[15]
DDRA_A[9]
DDRA_A[10]
DDR_DQ[11]
URSA_DQ[18]
DDRB_A[12]
DDR_DQ[10]
DDR_DQ[16-31]
DDR_DQ[5]
DDRB_A[9]
URSA_DQ[17]
DDRA_A[10]
DDRA_A[12]
DDR_DQ[4]
URSA_DQ[30]
URSA_DQ[12]
DDRB_A[4]
DDR_DQ[9]
DDR_DQ[29]
DDR_DQ[0]
URSA_DQ[24]
URSA_DQ[4]
URSA_A[6]
DDR_DQ[16]
DDRA_A[6]
DDRA_A[3]
DDR_DQ[20]
DDRA_A[0-12]
DDR_DQ[13]
DDR_DQ[17]
URSA_A[12]
URSA_DQ[6]
URSA_DQ[2]
URSA_A[0]
URSA_DQ[22]
DDRA_A[7]
URSA_DQ[10]
DDR_DQ[12]
DDR_DQ[22]
DDR_DQ[28]
DDRB_A[7]
DDRA_A[4]
URSA_DQ[29]
URSA_A[10]
URSA_A[12]
URSA_DQ[20]
URSA_DQ[26]
DDRA_A[2]
URSA_A[9]
DDRB_A[6]
DDR_DQ[2]
DDR_DQ[19]
URSA_A[9]
DDRB_A[4]
DDRA_A[8]
URSA_A[11]
URSA_A[6]
DDR_DQ[6]
DDR_DQ[13]
DDR_DQ[14]
DDR_DQ[8]
DDRB_A[6]
DDR_DQ[11]
DDR_DQ[18]
URSA_DQ[28]
DDR_DQ[16]
DDR_DQ[30]
URSA_DQ[9]
DDR_DQ[27]
DDRB_A[11]
DDR_DQ[0]
DDR_DQ[0-15]
URSA_DQ[19]
DDRB_A[11]
URSA_DQ[21]
DDRB_A[7]
DDRA_A[5]
URSA_A[7]
DDRB_A[3]
DDRA_A[7]
DDR_DQ[28]
DDR_DQ[25]
DDR_DQ[25]
DDR_DQ[26]
DDR_DQ[23]
DDR_DQ[15]
URSA_DQ[0]
URSA_DQ[16]
DDR_DQ[5]
DDR_DQ[2]
DDRA_A[1]
DDRA_A[0]
DDR_DQ[20]
DDR_DQ[15]
DDR_DQ[18]
URSA_DQ[13]
DDR_DQ[21]
DDRA_A[6]
DDR_DQ[10]
DDR_DQ[26]
DDRA_A[12]
DDRB_A[12]
DDRA_A[3]
DDR_DQ[1]
URSA_DQ[11]
DDRB_A[0-12]
URSA_A[4]
DDR_DQ[31]
URSA_A[10]
DDRB_A[8]
DDRB_A[2]
URSA_A[2]
URSA_DQ[14]
DDRA_A[11]
DDR_DQ[30]
DDR_DQ[24]
URSA_A[5]
DDR_DQ[29]
DDRB_A[9]
URSA_DQ[25]
DDRA_A[4]
URSA_A[4]
URSA_A[2]
DDRA_A[5]
DDRB_A[0]
DDR_DQ[9]
URSA_DQ[27]
DDRB_A[2]
URSA_A[3]
DDR_DQ[22]
URSA_A[1]
DDR_DQ[7]
DDR_DQ[7]
DDR_DQ[3]
DDRB_A[1]
DDR2 1.8V By CAP - Place these Caps near Memory
PI Result
resonance Compensation
C
2009
FRC DDR
USB_OCD
0.1uF
C1244
USB_CTL
USB_DP
001:AR34
USB_DM
001:AR34
+5V_EXT
10K
R1250
R1250
100
R1201
BG2012B080TF
L1202
+3.3V_ST
5.6B
D1240
SDA_SUB/AMP
001:AI5;006:D12
IR
001:AB22;004:AD4
100
R1200
0.
1u
F
C1204
5.6B
D1238
0
R1230
KEY1
001:AB23
5.6B
D1239
100pF
50V
C1207
KEY2
001:AB23
1000pF
50V
C1205
BG2012B080TF
L1204
BG2012B080TF
L1203
LED_MOVING/LED_R
001:AR32
+3.3V_ST
0.1uF
16V
C1200
0.
1u
F
C1203
0
R1229
1000pF
50V
C1201
+5V_ST
0.1uF
16V
C1202
SCL_SUB/AMP
001:AI5;006:D11
180
R1209
47
R1226
MIC2009YM6-TR
IC1202
3
ENABLE
2
GND
4
FAULT/
1
VIN
6
VOUT
5
ILIMIT
0.1uF
16V
C1208
CDS3C05HDMI1
5.6V
D1203
4.7K
R1203
4.7K
R1202
CB3216PA501E
L1200
CB3216PA501E
L1201
2SC3052
Q1202
E
B
C
+3.3V_ST
4.7K
R1227
10K
R1228
CB3216PA501E
L1219
+3.3V
4.7K
R1219
OPT
0.1uF
OPT
C1253
LED_B
120K
OPT
R1213
0
R1225
OPT
0
CL40
R1214
0
R1239
Except_CL40
12507WS-12L
P1200
1
SCL
2
SDA
3
GND
4
KEY1
5
KEY2
6
5V_ST
7
GND
8
WARM_ST
9
IR
10
GND
11
3.3V_ST
12
PWR_ON
13
GND
10uF
10V
C1245
100
R1231
OPT
USB DOWN STREAM
KJA-UB-4-0004
JK1204
1
2
3
4
5
+5V_USB_1
001:I2
+5V_USB_1
001:I2
ENKMC2838-T112
D1204
A1
C
A2
0
R1220
0
R1221
LED_MOVING/LED_R
001:AR32
0
R1222
LED_B
001:AR32
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
10K
R1223
10K
R1224
OPT
+3.3V_ST
ADMC5M03200L_AMODIODE
5.6V
D1201
ADMC5M03200L_AMODIODE
5.6V
D1202
ADMC5M03200L_AMODIODE
5.6V
D1232
OPT
ADMC5M03200L_AMODIODE
5.6V
D1233
OPT
330uF
25V
C1209
100pF
50V
C1249
100pF
50V
C1248
[CONTROL IR & LED]
Pin to Pin Replacable with T-MIC2019YM6
USB
USB +5V Over Current Protection --> USB Jack
USB JACK
For testing CL40 & Small model
C
2009
ETC SUB BOARD I /F
Feb., 2009
P/NO : MFL41946813
