LG 22LV2300-ZG (CHASSIS:LD01R) Service Manual ▷ View online
- 21 -
12. AV Audio
Check AV Cable for damage
for damage or open conductor.
Check JK1604 & Signal Line.
ok
ok
No
Replace Jack.
Follow procedure
’9. All source audio’
trouble shooting guide.
13. Component/ SCART Audio
Check Component Cable
for damage or open conductor.
Check JK1602, JK1603
& Signal Line.
ok
ok
No
Replace Jack.
Follow procedure
’9. All source audio’
trouble shooting guide.
14. RGB Audio
Check Cable conductors
for damage or open conductor.
Check JK1102 & Signal Line.
ok
No
ok
Replace Jack.
Follow procedure
’9. All source audio’
trouble shooting guide.
- 22 -
BLOCK DIAGRAM
RGB PC
SPDIF
Component1
H/P OUT
HDMI1/2(DVI)
S
I2176
S
I2176
(LG
IT)
(LG
IT)
PC/DVI A
udi
In
RS-232
C
IF
+/-
TU_CVBS
SIF
L/R
S7LR
IC101
M
A
X
323
2
M
A
X
323
2
S
E
R
IAL
F
L
AS
H
IC14
01 (8
M
bit)
M
X
25
L
80
05M
2I
S
E
R
IAL
F
L
AS
H
IC14
01 (8
M
bit)
M
X
25
L
80
05M
2I
LVDS
(FHD/5
0Hz)
A
u
dio
A
M
P
NTP7400
USB2.0
DP
/D
M
SPK L/R
X-ta
l
24
M
FPC(5
1P)
I2S
SP
DI
F
H/
P L/R
CV
BS
, Y/
Pb
/P
r,
L
/R
RGB/
H/V
R
S
23
2C
Rear
TMDS
DD
R3 Add.
DD
R3 Dat
a
SP
I
AV
2
Side
N
A
ND FL
A
S
H
IC10
2 (1Gbit
)
P
C
M_A[0:7]
TMDS
HDMI3
CV
BS
, L
/R
DDR3 1
G
b
IC
1202
H
5TQ1G63BF
R
DDR3 1
G
b
IC
1201
H
5TQ1G63BF
R
CONTROL
IR
& LED /
SOFT TOUC
H
(T
A
C
T SWI
TCH)
SE
NS
O
R
_S
CL/S
D
A
LE
D_
R
KE
Y1
KE
Y2
IR
LE
D_
B
SOFT TOUC
H
_S
CL/S
D
A
M24M
0
1-HRMN6T
P
IC
104
256
K
b
it
I2C
AV
2
CV
BS
, L
/R
Option
F-SC
A
R
T
SC1_CVBS_IN
SC1_R/G/B
FE_VOUT
CI Slot
74L
C
X
244
Bu
ffe
r
TS_
D
A
T
A[0:7]
P
C
M
_D
A
T
A
[0:7]
FE_
T
S_
D
A
T
A
[0:7]
PCM_
A
[8
:14
]
- 23 -
300
200
540
400
900
800
521
A4
LV
1
120
500
51
1
510
A5
A2
A21
A6
A10
EXPLODED VIEW
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
IMPORTANT SAFETY NOTICE
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
FRC_DQU[5]
FRC_DQU[0]
FRC_DQL[0]
FRC_DQU[7]
FRC_A[0]
FRC_DQL[1]
FRC_DQU[4]
FRC_A[6]
FRC_A[10]
FRC_A[4]
FRC_DQL[5]
FRC_A[2]
FRC_A[8]
FRC_A[9]
FRC_A[7]
FRC_A[1]
FRC_A[5]
FRC_A[3]
FRC_DQU[6]
FRC_A[11]
FRC_DQL[2]
FRC_A[12]
FRC_DQU[2]
FRC_A[13]
FRC_DQL[4]
FRC_DQL[3]
FRC_DQU[1]
FRC_DQL[7]
FRC_DQU[3]
FRC_DQL[6]
SPI_DO
AVDD_LVDS_3.3V_M
+1.26V_FRC
PWM1
C126
0.1uF
0.1uF
R112
10K
OPT
AVDD33_M
DVDD_DDR_1V_M
AVDD_PLL_M
R105
10K
R115
10K
OPT
C135
0.1uF
AVDD_PLL_M
SPI_SCLK
VDDC10_M
C132
0.1uF
0.1uF
C128
0.1uF
0.1uF
C123
0.1uF
0.1uF
SCL_URSA
VDDC10_M
C102
22uF
10V
22uF
10V
2D/3D_CTL
C124
0.1uF
0.1uF
+3.3V_FRC
C121
0.1uF
0.1uF
R106
10K
OPT
R113
10K
OPT
FRC_DQSL
URSA_MODEL_OPT_1
AVDD33_M
C134
0.1uF
0.1uF
C117
0.1uF
0.1uF
C101
0.1uF
0.1uF
SPI_DI
C110
0.1uF
0.1uF
R154
33
R104
10K
OPT
+1.5V_FRC_DDR_M
R147
1M
R107
10K
OPT
VDD33_M
C105
0.1uF
0.1uF
DVDD_DDR_1V_M
SPI_SCLK
FRC_CASB
C109
0.1uF
0.1uF
+3.3V_FRC
R102
10K
OPT
+3.3V_FRC
FRC_MCLK
SDA_URSA
R111
10K
OPT
SDA_DEBUG
C129
0.1uF
0.1uF
FRC_DQL[0-7]
+3.3V_FRC
FRC_DQSU
URSA_MODEL_OPT_0
FRC_RASB
SCL_DEBUG
FRC_BA0
C111
0.1uF
0.1uF
R134
33
AVDD_PLL_M
URSA_MODEL_OPT_0
FRC_DQSUB
FRC_WEB
PWM0
R101
10K
GPIO[1]
C122
0.1uF
0.1uF
R114
10K
OPT
PWM0
C119
0.1uF
0.1uF
R123
4.7K
R110
10K
OPT
SDA_DEBUG
GPIO[8]
FRC_ODT
R108
10K
C113
0.1uF
0.1uF
+3.3V_FRC
VDD33_M
FRC_DQSLB
C133
0.1uF
0.1uF
R109
10K
OPT
C107
0.1uF
0.1uF
AVDD_LVDS_3.3V_M
VDDC10_M
URSA_MODEL_OPT_1
+3.3V_FRC
R118
22
URSA5_DEBUG
2D/3D_CTL
+1.26V_FRC
AVDD_LVDS_3.3V_M
FRC_DML
R153
33
SPI_CS
FRC_A[0-13]
C130
0.1uF
0.1uF
SPI_DO
R116
10K
OPT
R103
10K
C131
0.1uF
0.1uF
SPI_CS
C125
0.1uF
0.1uF
+3.3V_FRC
C116
0.1uF
0.1uF
FRC_BA1
URSA_MODEL_OPT_2
VDD33_M
FRC_DQU[0-7]
C106
0.1uF
0.1uF
URSA_MODEL_OPT_2
C115
0.1uF
0.1uF
C118
0.1uF
0.1uF
FRC_MCLKB
SDA_URSA
FRC_DMU
FRC_CKE
R117
22
URSA5_DEBUG
R124
10K
PWM1
+3.3V_FRC
SCL_URSA
AVDD33_M
GPIO[1]
R133
33
R126
3.3K
SCL_DEBUG
C103
22uF
10V
22uF
10V
SPI_DI
GPIO[8]
FRC_BA2
C104
0.22uF
6.3V
0.22uF
6.3V
C108
0.22uF
6.3V
0.22uF
6.3V
C120
0.22uF
6.3V
0.22uF
6.3V
R119
0
0
URSA5_MP
R120
0
URSA5_MP
C137
13pF
C136
13pF
C114
22uF
10V
22uF
10V
FRC_DDR3_RESETB
FRC_RESET
R162
33
I2C_SDA
I2C_SCL
SCL_DEBUG
SCL_URSA_S
SCL_URSA_M
SDA_URSA_M
SDA_URSA_S
SDA_DEBUG
R121
0
0
URSA5_MP
R122
0
URSA5_MP
SCL_URSA_M
R127
4.7K
SDA_URSA_M
R129
33
+3.3V_FRC
R130
33
R128
4.7K
SOFT_RST_R_S
C138
220pF
50V
R148
4.7K
R150
1K
S_M_PIF_FC
S_M_PIF_FC_S
OP_SYNC_R_S
OP_SYNC_R
R151
1K
R149
1K
S_M_PIF_CLK
S_M_PIF_CS_S
SOFT_RST_R
S_M_PIF_CLK_S
R152
1K
S_M_PIF_CS
S_M_PIF_DA1_S
S_M_PIF_DA0
S_M_PIF_DA0_S
S_M_PIF_DA1
XTAL_M_OUT
+3.3V_FRC
L/DIM0_VS
L/DIM0_MOSI
L/DIM0_SCLK
LPLL_REFIN_S
+3.3V_FRC
LPLL_REFIN
R161
4.7K
OPT
OPT
R158
4.7K
OPT
OPT
LPLL_REFIN_S
R160
4.7K
OPT
OPT
R159
4.7K
OPT
OPT
RXBCLKN
RXB3P
RXB4P
RXB0P
RXB2P
RXB4N
RXB1P
RXB1N
RXB2N
RXB0N
RXB3N
RXBCLKP
RXA0N
RXA2P
RXA0P
RXA1P
RXA3N
RXACLKP
RXACLKN
RXA1N
RXA3P
RXA4N
RXA2N
RXA4P
URSA5_SLAVE_RESET
R163
33
L/DIM1_MOSI
L/DIM1_SCLK
R135
200
EXT_TERMI_200
R144
200
EXT_TERMI_200
R146
200
EXT_TERMI_200
R136
200
EXT_TERMI_200
R143
200
EXT_TERMI_200
R142
200
EXT_TERMI_200
R141
200
EXT_TERMI_200
R139
200
EXT_TERMI_200
R137
200
EXT_TERMI_200
R138
200
EXT_TERMI_200
R145
200
EXT_TERMI_200
R140
200
EXT_TERMI_200
TXC1N
TXC3P
TXD0P
TXD1N
TXD0N
TXDCLKN
TXD4P
TXC0N
TXC0P
TXD1P
TXD2N
TXCCLKN
TXDCLKP
TXC3N
TXD2P
TXD4N
TXCCLKP
TXC1P
TXD3P
TXD3N
TXC2P
TXC2N
TXC4P
TXC4N
TXA3P
TXBCLKP
TXA2P
TXB0P
TXB1N
TXA4P
TXB0N
TXB3N
TXA4N
TXACLKN
TXB4P
TXB3P
TXA0P
TXA2N
TXA1N
TXB1P
TXA0N
TXA1P
TXB2N
TXBCLKN
TXB4N
TXACLKP
TXB2P
TXA3N
+1.5V_FRC_DDR_M+1.5V_FRC_DDR_M
SLAVE_GPIO[8]
R164
0
R165
0
R166
0
R167
0
R168
0
R131
3.9K
OPT
R132
3.9K
OPT
R169
10
10
R170
10
R171
10
R125
10
R156
33
R157
33
R155
33
C112
1uF
10V
1uF
10V
C127
2.2uF
10V
2.2uF
10V
R136-*2 120
EXT_TERMI_120
R144-*3 150
EXT_TERMI_150
R135-*2 120
EXT_TERMI_120
R141-*2 120
EXT_TERMI_120
R145-*3 150
EXT_TERMI_150
R139-*2 120
EXT_TERMI_120
R146-*1 100
EXT_TERMI_100
R140-*3 150
EXT_TERMI_150
R143-*2 120
EXT_TERMI_120
R145-*2 120
EXT_TERMI_120
R141-*3 150
EXT_TERMI_150
R136-*3 150
EXT_TERMI_150
R140-*2 120
EXT_TERMI_120
R146-*3 150
EXT_TERMI_150
R139-*1 100
EXT_TERMI_100
R137-*2 120
EXT_TERMI_120
R141-*1 100
EXT_TERMI_100
R139-*3 150
EXT_TERMI_150
R142-*2 120
EXT_TERMI_120
R144-*1 100
EXT_TERMI_100
R138-*1 100
EXT_TERMI_100
R138-*3 150
EXT_TERMI_150
R144-*2 120
EXT_TERMI_120
R142-*1 100
EXT_TERMI_100
R136-*1 100
EXT_TERMI_100
R143-*1 100
EXT_TERMI_100
R146-*2 120
EXT_TERMI_120
R135-*3 150
EXT_TERMI_150
R135-*1 100
EXT_TERMI_100
R137-*3 150
EXT_TERMI_150
R140-*1 100
EXT_TERMI_100
R138-*2 120
EXT_TERMI_120
R142-*3 150
EXT_TERMI_150
R137-*1 100
EXT_TERMI_100
R143-*3 150
EXT_TERMI_150
R145-*1 100
EXT_TERMI_100
P101
12507WR-04L
URSA5_DEBUG
1
2
3
4
5
L101
CIC21J501NE
L103
CIC21J501NE
L104
CIC21J501NE
L106
CIC21J501NE
L102
CIC21J501NE
L105
CIC21J501NE
SW5201
JS2235S
URSA5_DEBUG_SWITCH
3
2
1
4
5
6
SW102
JS2235S
URSA5_DEBUG_SWITCH
3
2
1
4
5
6
X101
24MHz
IC101
LGE7303C
DDR3_A0/DDR2_NC
P14
DDR3_A1/DDR2_A8
G15
DDR3_A2/DDR2_NC
N14
DDR3_A3/DDR2_A10
L15
DDR3_A4/DDR2_A2
H15
DDR3_A5/DDR2_A3
L14
DDR3_A6/DDR2_A4
G14
DDR3_A7/DDR2_A5
N12
DDR3_A8/DDR2_A6
G13
DDR3_A9/DDR2_A9
N13
DDR3_A10/DDR2_RASZ
H14
DDR3_A11/DDR2_A11
F15
DDR3_A12/DDR2_A0
H13
DDR3_A13/DDR2_A12
P13
DDR3_BA0/DDR2_BA2
M12
DDR3_BA1/DDR2_CASZ
H12
DDR3_BA2/DDR2_A1
L13
DDR3_MCLK/DDR2_MCLK
F16
DDR3_MCLKZ/DDR2_MCLKZ
F17
DDR3_CKE/DDR2_ODT
J13
DDR3_ODT/DDR2_CKE
K12
DDR3_RASZDDR2_WEZ
L12
DDR3_CASZ/DDR2_BA1
K13
DDR3_WEZ/DDR2_BA0
K14
DDR3_RESET/DDR2_A7
M14
DDR3_DQSL/DDR2_DQSL
N16
DDR3_DQSU/DDR2_DQSU
M17
DDR3_DQSBL/DDR2_DQSBL
M16
DDR3_DQSBU/DDR2_DQSBU
M15
DDR3_DQML/DDR2_DQU5
J15
DDR3_DQMU/DDR2_DQU4
R16
DDR3_DQL0/DDR2_DQU3
R17
DDR3_DQL1/DDR2_DQL0
H17
DDR3_DQL2/DDR2_DQL6
R15
DDR3_DQL3/DDR2_DQL7
J17
DDR3_DQL4/DDR2_DQL3
T17
DDR3_DQL5/DDR2_DQL2
H16
DDR3_DQL6/DDR2_DQL1
T15
DDR3_DQL7/DDR2_DQL5
G16
DDR3_DQU0/DDR2_DQU7
K15
DDR3_DQU1/DDR2_DQML
N15
DDR3_DQU2/DDR2_DQU2
K17
DDR3_DQU3/DDR2_DQU6
P17
DDR3_DQU4/DDR2_NC
L17
DDR3_DQU5/DDR2_DQU1
P16
DDR3_DQU6/DDR2_DQU0
K16
DDR3_DQU7/DDR2_DQMU
P15
I2CM_SCL
D14
I2CM_SDA
D15
I2CS_SCL
P1
I2CS_SDA
P2
DDR3_NC/DDR2_A13
F14
DDR3_NC/DDR2_DQL4
T16
VSS_1
D6
VSS_2
D7
VSS_3
D8
VSS_4
D9
VSS_5
E6
VSS_6
E7
VSS_7
E8
VSS_8
E9
VSS_9
E10
VSS_10
E16
VSS_11
F3
VSS_12
F6
VSS_13
F7
VSS_14
F8
VSS_15
F9
VSS_16
G1
VSS_17
G2
VSS_18
G4
VSS_19
G5
VSS_20
G6
VSS_21
G7
VSS_22
G8
VSS_23
G9
VSS_24
G17
VSS_25
H1
VSS_26
H2
VSS_27
H4
VSS_28
H5
VSS_29
H6
VSS_30
H7
VSS_31
H8
VSS_32
H9
VSS_33
H10
VSS_34
H11
VSS_35
J4
VSS_36
J5
VSS_37
J6
VSS_38
J7
VSS_39
J8
VSS_40
J9
VSS_41
J10
VSS_42
J11
VSS_43
J12
VSS_44
J14
VSS_45
J16
VSS_46
K4
VSS_47
K5
VSS_48
K6
VSS_49
K7
VSS_50
K8
VSS_51
K11
VSS_52
L6
VSS_53
L7
VSS_54
L8
VSS_55
L11
VSS_56
L16
VSS_57
M6
VSS_58
M7
VSS_59
M8
VSS_60
M11
VSS_61
M13
VSS_62
N6
VSS_63
N7
VSS_64
N8
VSS_65
N17
VSS_66
P3
VSS_67
P4
VSS_68
P5
VSS_69
P6
VSS_70
P7
VSS_71
P12
VSS_72
U16
NC
L9
HW_RESET
J3
TESTPIN_1
D1
TESTPIN_2
D2
TESTPIN_3
D3
TESTPIN_4
E1
TESTPIN_5
E2
TESTPIN_6
E3
TESTPIN_7
F1
TESTPIN_8
F2
M0_SCLK
C17
M0_MOSI
D16
M1_SCLK
D17
M1_MOSI
E15
M2_SCLK
E14
M2_MOSI
E13
M3_SCLK
E12
M3_MOSI
F13
SPI_CK
T9
SPI_CZ
U10
SPI_DI
U9
SPI_DO
T10
TXA0P/GCLK6/BLUE[7]
C8
TXA0N/GCLK5/BLUE[6]
C9
TXA1P/OPT_N/LK3/BLUE[9]
B8
TXA1N/FLK/BLUE[8]
A8
TXA2P/GREEN[1]
A7
TXA2N/OPT_P/LK2/GREEN[0]
B7
TXACLKP/RLV0N/GREEN[3]
C6
TXACLKN/RLV0P/GREEN[2]
C7
TXA3P/RLV1N/GREEN[5]
B6
TXA3N/RLV1P/GREEN[4]
A6
TXA4P/RLV2N/GREEN[7]
A5
TXA4N/RLV2P/GREEN[6]
B5
TXB0P/RLV3N/GREEN[9]
C4
TXB0N/RLV3P/GREEN[8]
C5
TXB1P/RLVCLKN/RED[1]
B4
TXB1N/RLVCLKP/RED[0]
A4
TXB2P/RLV4P/RED[3]/EPI_A3P
A3
TXB2N/RLV4N/RED[2]/EPI_A3N
B3
TXBCLKP/RLV5N/RED[5]/EPI_A2P
C2
TXBCLKN/RLV5P/RED[4]/EPI_A2N
C3
TXB3P/RLV6N/RED[7]/EPI_A1P
B2
TXB3N/RLV6P/RED[6]/EPI_A1N/
A2
TXB4P/RLV7N/RED[9]/EPI_A0P
C1
TXB4N/RLV7P/RED[8]/EPI_A0N
B1
TXC0P/SOE
C16
TXC0N/POL
B17
TXC1P/GSP_R
B16
TXC1N/GSP/VST
A16
TXC2P/GOE/GCLK1
A15
TXC2N/GSC/GCLK3
B15
TXCCLKP/LLV0N
C14
TXCCLKN/LLV0P
C15
TXC3P/LLV1N
B14
TXC3N/LLV1P
A14
TXC4P/LLV2N
A13
TXC4N/LLV2P
B13
TXD0P/LLV3N
C12
TXD0N/LLV3P
C13
TXD1P/LLVCLKN
B12
TXD1N/LLVCLKP
A12
TXD2P/LLV4N/EPI_B3P
A11
TXD2N/LLV4P/EPI_B3N
B11
TXDCLKP/LLV5N/BLUE[1]/EPI_B2P
C10
TXDCLKN/LLV5P/BLUE[0]/EPI_B2N
C11
TXD3P/LLV6N/BLUE[3]
B10
TXD3N/LLV6P/BLUE[2]/EPI_B1N
A10
TXD4P/LLV7N/BLUE[5]/EPI_B0P
A9
TXD4N/LLV7P/BLUE[4]/EPI_B0N
B9
MOD_GPIO0/VDD_ODD/HSYNC
D10
MOD_GPIO1/VDD_EVEN/VSYNC
D11
MOD_GPIO2/PWM13/GCLK4/LCK
D12
MOD_GPIO3/PWM14/GCLK2/LDE
D13
PWM0/SCAN_BLK1
U12
PWM1/SCAN_BLK2
T12
LPLL_FBCLK
G3
LPLL_OUTCLK
E17
LPLL_REFIN
H3
AVDD_1
F4
AVDD_2
F5
AVDD_DDR_C_1
F10
AVDD_DDR_C_2
G10
AVDD_DDR_D_1
F11
AVDD_DDR_D_2
F12
AVDD_DDR_D_3
G11
AVDD_DDR_D_4
G12
AVDD_LVDS3.3V_1
D4
AVDD_LVDS3.3V_2
D5
AVDD_LVDS3.3V_3
E4
AVDD_LVDS3.3V_4
E5
AVDD_MPLL3.3V
M5
AVDD_LPLL3.3V
L4
AVDD_PLL3.3V
L5
AVDDL_MOD1.26V
K10
DVDD_DDR_1.26V
L10
DVDD_HF1.26V
K9
VD33_1
M4
VD33_2
N4
VD33_3
N5
VDDC_1.26V_1
M9
VDDC_1.26V_2
M10
VDDC_1.26V_3
N9
VDDC_1.26V_4
N10
VDDC_1.26V_5
N11
VDDC_1.26V_6
P10
VDDC_1.26V_7
P11
RXBCLKP
R2
RXBCLKN
R3
RXB0P
R4
RXB0N
R5
RXB1P
T4
RXB1N
U4
RXB2P
U3
RXB2N
T3
RXB3P
T2
RXB3N
U2
RXB4P
T1
RXB4N
R1
RXACLKP
R6
RXACLKN
R7
RXA0P
R8
RXA0N
R9
RXA1P
T8
RXA1N
U8
RXA2P
U7
RXA2N
T7
RXA3P
T6
RXA3N
U6
RXA4P
U5
RXA4N
T5
XTALO
J1
XTALI
J2
GPIO0/(UART_RX/S_PIF_DA0)
R13
GPIO1
P9
GPIO2/(S_PIF_CLK)
T13
GPIO3/(LTD_DA1)
U15
GPIO4/(LTD_DE)
R14
GPIO5/(LTD_CLK)
K2
GPIO6/(LTD_DA0)
K1
GPIO7(3D_FLAG)
T14
GPIO8
P8
GPIO9/(UART_TX/S_PIF_DA1)
U14
GPIO10/(S_PIF_FC)
U13
GPIO11/(S_PIF_CS)
R12
VSYNC_LIKE
E11
M_S_PIF_CLK
N2
M_S_PIF_CS
M1
M_S_PIF_DA0
N1
M_S_PIF_DA1
N3
M_S_PIF_FC
M3
S_M_PIF_CLK
L1
S_M_PIF_CS
M2
S_M_PIF_DA0
L2
S_M_PIF_DA1
K3
S_M_PIF_FC
L3
SOFT_RST_L
R10
SOFT_RST_R
T11
OP_SYNC_L
R11
OP_SYNC_R
U11
IC102-*1
W25X40BVSSIG
URSA5_FLASH_WINBOND_4M
3
WP
2
DO[IO1]
4
GND
1
CS
5
DI[IO0]
6
CLK
7
HOLD
8
VCC
IC102
MX25L4006EM2I-12G
URSA5_FLASH_MACRONIX_4M
3
WP#
2
SO/SIO1
4
GND
1
CS#
5
SI/S
6
SCL
7
HOL
8
VCC
MASTER FRC
MStar URSA5
01
D13
GPIO1 : HI => B8/94, LOW => B4/98
LOW
MODEL_OPT_0
2D/3D_CTL
Debugging for URSA5
CHIP_CONF : {GPIO8, PWM1, PWM0}
CHIP_CONF = 3’d5 : boot from interal SRAM
CHIP_CONF = 3’d6 : boot from EEPROM
CHIP_CONF = 3’d7 : boot from SPI Flash
CHIP_CONF = 3’d5 : boot from interal SRAM
CHIP_CONF = 3’d6 : boot from EEPROM
CHIP_CONF = 3’d7 : boot from SPI Flash
PIN NO.
[SPI FLASH(4M&2Mbit)]
D11
D10
D12
RESERVED
MODEL_OPT_2
MODEL OPTION
(VDDP)
HIGH
PIN NAME
RESERVED
PLACE TERMINATION RESISTORS CLOSE TO URSA5
MODEL_OPT_1
URSA5 CONFIGURATION
Place Close to Bead
URSA5 H/W OPTION
L/DIM_96BLOCK
MASTER
ADDRESS:0xB4
L/DIM_72BLOCK
PIF GROUND SHIELD
MPIF/SPIF/LPLL pattern are need
same length.
same length.
Keep traces of LPLL_REFIN,LPLL_OUTCLK_S,
LPLL_FBCLK_S route equal length.
Termination resistors should be closed URSA5
LPLL_FBCLK_S route equal length.
Termination resistors should be closed URSA5
RESERVED
RESERVED
RESERVED
RESERVED
LVDS RX EXTERNAL TERMINATION RESISTOR MULTI OPTION
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