JBL MS 8 Service Manual ▷ View online
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAMx32_2.fm - Rev. J 12/08 EN
8
64Mb: x32 SDRAM
Pin/Ball Assignments and Descriptions
Figure 3:
90-Ball VFBGA (Top View, Ball Down)
1
2
3
4
6
7
8
9
5
DQ26
DQ28
V
SS
Q
V
SS
Q
V
DD
Q
V
SS
A4
A7
CLK
DQM1
V
DD
Q
V
SS
Q
V
SS
Q
DQ11
DQ13
DQ24
V
DD
Q
DQ27
DQ29
DQ31
DQM3
A5
A8
CKE
NC
DQ8
DQ10
DQ12
V
DD
Q
DQ15
V
SS
V
SS
Q
DQ25
DQ30
NC
A3
A6
NC
A9
NC
V
SS
DQ9
DQ14
V
SS
Q
V
SS
V
DD
V
DD
Q
DQ22
DQ17
NC
A2
A10
NC
BA0
CAS#
V
DD
DQ6
DQ1
V
DD
Q
V
DD
DQ21
DQ19
V
DD
Q
V
DD
Q
V
SS
Q
V
DD
A1
NC
RAS#
DQM0
V
SS
Q
V
DD
Q
V
DD
Q
DQ4
DQ2
DQ23
V
SS
Q
DQ20
DQ18
DQ16
DQM2
A0
BA1
CS#
WE#
DQ7
DQ5
DQ3
V
SS
Q
DQ0
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
MS-8
40
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAMx32_2.fm - Rev. J 12/08 EN
9
64Mb: x32 SDRAM
Pin/Ball Assignments and Descriptions
Table 4:
Pin/Ball Descriptions
86-Pin TSOP
Numbers
90-Ball VFBGA
Numbers
Symbol
Type
Description
68
J1
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input signals
are sampled on the positive edge of CLK. CLK also increments
the internal burst counter and controls the output registers.
are sampled on the positive edge of CLK. CLK also increments
the internal burst counter and controls the output registers.
67
J2
CKE
Input
Clock enable: CKE activates (HIGH) and deactivates (LOW) the
CLK signal. Deactivating the clock provides PRECHARGE power-
down and SELF REFRESH operation (all banks idle), ACTIVE
power-down (row active in any bank), or CLOCK SUSPEND
operation (burst/access in progress). CKE is synchronous except
after the device enters power-down and self refresh modes,
where CKE becomes asynchronous until after exiting the same
mode. The input buffers, including CLK, are disabled during
power-down and self refresh modes, providing low standby
power. CKE may be tied HIGH.
CLK signal. Deactivating the clock provides PRECHARGE power-
down and SELF REFRESH operation (all banks idle), ACTIVE
power-down (row active in any bank), or CLOCK SUSPEND
operation (burst/access in progress). CKE is synchronous except
after the device enters power-down and self refresh modes,
where CKE becomes asynchronous until after exiting the same
mode. The input buffers, including CLK, are disabled during
power-down and self refresh modes, providing low standby
power. CKE may be tied HIGH.
20
J8
CS#
Input
Chip select: CS# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when CS# is registered HIGH, but READ/WRITE bursts
already in progress will continue and DQM operation will retain
its DQ mask capability while CS# is HIGH. CS# provides for
external bank selection on systems with multiple banks. CS# is
considered part of the command code.
(registered HIGH) the command decoder. All commands are
masked when CS# is registered HIGH, but READ/WRITE bursts
already in progress will continue and DQM operation will retain
its DQ mask capability while CS# is HIGH. CS# provides for
external bank selection on systems with multiple banks. CS# is
considered part of the command code.
17, 18, 19
K8, K7, J9
WE#,
CAS#,
RAS#
Input
Command inputs: WE#, CAS#, and RAS# (along with CS#)
define the command being entered.
define the command being entered.
16, 71, 28, 59
K9, K1, F8, F2
DQM0–
DQM3
Input
Input/output mask: DQM is sampled HIGH and is an input
mask signal for write accesses and an output enable signal for
read accesses. Input data is masked during a WRITE cycle. The
output buffers are placed in a High-Z state (2-clock latency)
during a READ cycle. DQM0 corresponds to DQ0–DQ7; DQM1
corresponds to DQ8–DQ15; DQM2 corresponds to DQ16–DQ23;
and DQM3 corresponds to DQ24–DQ31. DQM0–DQM3 are
considered same state when referenced as DQM.
mask signal for write accesses and an output enable signal for
read accesses. Input data is masked during a WRITE cycle. The
output buffers are placed in a High-Z state (2-clock latency)
during a READ cycle. DQM0 corresponds to DQ0–DQ7; DQM1
corresponds to DQ8–DQ15; DQM2 corresponds to DQ16–DQ23;
and DQM3 corresponds to DQ24–DQ31. DQM0–DQM3 are
considered same state when referenced as DQM.
22, 23
J7, H8
BA0, BA1
Input
Bank address input(s): BA0 and BA1 define to which bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
25–27, 60–66,
24
G8, G9, F7, F3,
G1, G2, G3, H1,
H2, J3, G7
A0–A10
Input
Address inputs: A0–A10 are sampled during the ACTIVE
command (row-address A0–A10) and READ/WRITE command
(column-address A0–A7 with A10 defining auto precharge) to
select one location out of the memory array in the respective
bank. A10 is sampled during a PRECHARGE command to
determine whether all banks are to be precharged (A10 HIGH)
or bank selected by BA0, BA1 (LOW). The address inputs also
provide the op-code during a LOAD MODE REGISTER command.
command (row-address A0–A10) and READ/WRITE command
(column-address A0–A7 with A10 defining auto precharge) to
select one location out of the memory array in the respective
bank. A10 is sampled during a PRECHARGE command to
determine whether all banks are to be precharged (A10 HIGH)
or bank selected by BA0, BA1 (LOW). The address inputs also
provide the op-code during a LOAD MODE REGISTER command.
2, 4, 5, 7, 8, 10,
11, 13, 74, 76,
77, 79, 80, 82,
83, 85, 31, 33,
34, 36, 37, 39,
40, 42, 45, 47,
48, 50, 51, 53,
77, 79, 80, 82,
83, 85, 31, 33,
34, 36, 37, 39,
40, 42, 45, 47,
48, 50, 51, 53,
54, 56
R8, N7, R9, N8,
P9, M8, M7, L8,
L2, M3, M2, P1,
L2, M3, M2, P1,
N2, R1, N3, R2,
E8, D7, D8, B9,
C8, A9, C7, A8,
A2, C3, A1, C2,
E8, D7, D8, B9,
C8, A9, C7, A8,
A2, C3, A1, C2,
B1, D2, D3, E2
DQ0–
DQ31
DQ31
Input/
Output
Data I/Os: Data bus.
MS-8
41
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAMx32_2.fm - Rev. J 12/08 EN
10
64Mb: x32 SDRAM
Functional Description
Functional Description
In general, this 64Mb SDRAM (512K x 32 x 4 banks) is a 4-bank DRAM that operates at
3.3V and includes a synchronous interface (all signals are registered on the positive edge
of the clock signal, CLK). Each of the 16,777,216-bit banks is organized as 2,048 rows by
256 columns by 32 bits.
3.3V and includes a synchronous interface (all signals are registered on the positive edge
of the clock signal, CLK). Each of the 16,777,216-bit banks is organized as 2,048 rows by
256 columns by 32 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1
select the bank, A0–A10 select the row). The address bits (A0–A7) registered coincident
with the READ or WRITE command are used to select the starting column location for
the burst access.
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1
select the bank, A0–A10 select the row). The address bits (A0–A7) registered coincident
with the READ or WRITE command are used to select the starting column location for
the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections
provide detailed information covering device initialization, register definition,
command descriptions, and device operation.
provide detailed information covering device initialization, register definition,
command descriptions, and device operation.
Initialization
SDRAMs must be powered up and initialized in a predefined manner. Operational
procedures other than those specified may result in undefined operation. After power is
applied to V
procedures other than those specified may result in undefined operation. After power is
applied to V
DD
and V
DD
Q (simultaneously) and the clock is stable (stable clock is
defined as a signal cycling within timing constraints specified for the clock pin), the
SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND
INHIBIT or NOP. Starting at some point during this 100µs period, and continuing at least
through the end of this period, COMMAND INHIBIT or NOP commands must be
applied.
SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND
INHIBIT or NOP. Starting at some point during this 100µs period, and continuing at least
through the end of this period, COMMAND INHIBIT or NOP commands must be
applied.
When the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP
command having been applied, a PRECHARGE command should be applied. All banks
must then be precharged, thereby placing the device in the all banks idle state.
command having been applied, a PRECHARGE command should be applied. All banks
must then be precharged, thereby placing the device in the all banks idle state.
3, 9, 35, 41, 49,
55, 75, 81
B2, B7, C9, D9,
E1, L1, M9, N9,
P2, P7
V
DD
Q
Supply
DQ power supply: Isolated on the die for improved noise
immunity.
immunity.
6, 12, 32, 38,
46, 52, 78, 84
B8, B3, C1, D1,
E9, L9, M1, N1,
P3, P8
V
SS
Q
Supply
DQ ground: Provide isolated ground to DQs for improved noise
immunity.
immunity.
1, 15, 29, 43
A7, F9, L7, R7
V
DD
Supply
Power supply: +3.3V ±0.3V. (See note 27 on page 50.)
44, 58, 72, 86
A3, F1, L3, R3
V
SS
Supply
Ground.
14, 21, 30, 57,
69, 70, 73
E3, E7, H3, H7,
K2, K3, H9
NC
–
No connect: These pins/balls should be left unconnected. Pin 70
is reserved for SSTL reference voltage supply. H7 is a no connect
for this part but may be used as A12 in future designs. H9 is used
as A11 in 128Mb, 256Mb, and 512Mb x32 FBGAs. PCB designs
that accommodate different densities must account for A11 with
stuffing options.
is reserved for SSTL reference voltage supply. H7 is a no connect
for this part but may be used as A12 in future designs. H9 is used
as A11 in 128Mb, 256Mb, and 512Mb x32 FBGAs. PCB designs
that accommodate different densities must account for A11 with
stuffing options.
Table 4:
Pin/Ball Descriptions (continued)
86-Pin TSOP
Numbers
90-Ball VFBGA
Numbers
Symbol
Type
Description
MS-8
42
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAMx32_2.fm - Rev. J 12/08 EN
11
64Mb: x32 SDRAM
Functional Description
When in the idle state, at least two AUTO REFRESH cycles must be performed. After the
AUTO REFRESH cycles are complete, the SDRAM is ready for mode register program-
ming. Because the mode register will power up in an unknown state, it must be loaded
prior to applying any operational command. If desired, the two AUTO REFRESH
commands can be issued after the LOAD MODE REGISTER command.
AUTO REFRESH cycles are complete, the SDRAM is ready for mode register program-
ming. Because the mode register will power up in an unknown state, it must be loaded
prior to applying any operational command. If desired, the two AUTO REFRESH
commands can be issued after the LOAD MODE REGISTER command.
The recommended power-up sequence for SDRAMs:
1. Simultaneously apply power to V
DD
and V
DD
Q.
2. Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTL-
compatible.
3. Provide stable CLOCK signal. Stable clock is defined as a signal cycling within timing
constraints specified for the clock pin.
4. Wait at least 100µs prior to issuing any command other than a COMMAND INHIBIT
or NOP.
5. Starting at some point during this 100µs period, bring CKE HIGH. Continuing at least
through the end of this period, 1 or more COMMAND INHIBIT or NOP commands
must be applied.
must be applied.
6. Perform a PRECHARGE ALL command.
7. Wait at least
7. Wait at least
t
RP time; during this time,0 NOPs or DESELECT commands must be
given. All banks will complete their precharge, thereby placing the device in the all
banks idle state.
banks idle state.
8. Issue an AUTO REFRESH command.
9. Wait at least
9. Wait at least
t
RFC time, during which only NOPs or COMMAND INHIBIT commands
are allowed.
10. Issue an AUTO REFRESH command.
11. Wait at least
11. Wait at least
t
RFC time, during which only NOPs or COMMAND INHIBIT commands
are allowed.
12. The SDRAM is now ready for mode register programming. Because the mode register
will power up in an unknown state, it should be loaded with desired bit values prior to
applying any operational command. Using the LMR command, program the mode
register. The mode register is programmed via the MODE REGISTER SET command
with BA1 = 0, BA0 = 0 and retains the stored information until it is programmed again
or the device loses power. Not programming the mode register upon initialization will
result in default settings which may not be desired. Outputs are guaranteed High-Z
after the LMR command is issued. Outputs should be High-Z already before the LMR
command is issued.
applying any operational command. Using the LMR command, program the mode
register. The mode register is programmed via the MODE REGISTER SET command
with BA1 = 0, BA0 = 0 and retains the stored information until it is programmed again
or the device loses power. Not programming the mode register upon initialization will
result in default settings which may not be desired. Outputs are guaranteed High-Z
after the LMR command is issued. Outputs should be High-Z already before the LMR
command is issued.
13. Wait at least
t
MRD time, during which only NOP or DESELECT commands are
allowed.
At this point the DRAM is ready for any valid command.
Note:
If desired, more than two AUTO REFRESH commands can be issued in the sequence.
After steps 9 and 10 are complete, repeat them until the desired number of AUTO
REFRESH +
After steps 9 and 10 are complete, repeat them until the desired number of AUTO
REFRESH +
t
RFC loops is achieved.
MS-8
43
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