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Digital Audio can be either PCM 2-channel data or one of the compressed data formats. It enters the unit 
on one of the digital input connectors that are connected to the Audio FPGA. The FPGA functions as a 
mux and routes the output NRZ, (Non Return to Zero) data of the connector selected by the user to the 
two Digital Receivers, Main and Zone. These receivers lock to the incoming signal and extract a 
2-channel PCM audio signal that is returned to the Audio FPGA. 

The Main Audio Data Path is as follows: 

1.  Output of the Main Digital Receiver and the Main ADC to the Audio FPGA 

2.  Output of the Audio FPGA to the Crystal 49400 Decoder on the Decoder Board, Daughter Board 0 

3.  Four 2-channel outputs from the Crystal 49400 Decoder back to the Audio FPGA 

4.  The four 2-channel streams are packed into a single octal data stream in the Audio FPGA 

5.  The output of the octal packer is sent to SHARC A on the DSP Board 

6.  The octal output of SHARC B is sent to the input of Sharc C 

7.  Two octal outputs of SHARC D are sent back to the Audio FPGA on the Main board 

8.  The two octal outputs from SHARC D (not all slots are used) are unpacked into four 2-channel PCM 

streams in the Audio FPGA 

9. These 

four 

2-channel 

streams are sent to the Analog board as MAIN_DAC(0:4)_SDI. 

CRYSTAL DECOER CS49400

AUDIO CLOCKS & DATA

4 STEREO IN TO 1 OCTAL OUT

SHARC DSP A/B AUDIO DATA IN

SHARC DSP C/D AUDIO DATA I/O

1 OCTAL IN TO 4 STEREO OUT

MAIN_DRCVR_SDO

MAIN_ADC_SDO

DECODER_SDO(0:3)

DSP D Serial Audio Out

MAIN_DAC(0:5)_SDI

SHARC

DSP

C/D

SHARC

DSP

AB

DSPA_OA_SDI

CRYSTAL

49400

DECODER

DECODER_SDI

DSPB_SDI

 

 

 

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There are two possible sources of master clock for the Main Audio Path. The 24.576 oscillator that can 
provide either a 48kHz or 96kHz sample rate, or the master clock output of the main digital receiver. In 
practice, the unit runs off the crystal at 96kHz when the input is analog. When the input is digital, the 
master clock output of the digital receiver is used. This master clock is de-jittered by the PLL that is 
controlled by the I/O FPGA using signals derived from MAIN_DRCVR_MCKO. 

Depending on the input selected, the appropriate master clock is routed from the I/O FPGA to the Audio 
FPGA. Here it drives a clock tree that divides down the master clock, which is 256 times the sample rate, 
256FS, to create the other clock rates required. 

•  The SHARC DSPs receive a word clock, or framing signal, FS and a bit clock of 256FS 
•  The Digital Receiver, ADCs and DACs use a word clock, FS/and bit clock, 64FS/ 
•  The DSP and Decoder Boards receive a 256FS Master Clock and a word clock, FS/. These are used 

on each individual board to derive the audio clock signals required by that particular board. 

 

MAIN DRCVR

MAIN_DRCVR_MCKO

24.576 MHZ

4896_MCK

PLL

PLL_MCKO

PLLMCKO

MAIN_MCKO

MAIN

DRCVR

MAIN_DRCVR_FSI

MAIN_DRCVR_SCKI

MAIN

ANALOG

MAIN_ANLG_FSI

MAIN_ANLG_SCKI

DAUGHTER

BOARDS

0,1,2

DBx_FSI

DBx_MCKI

PLL

CONTROL

MAIN_ANLG_MCKI

DSP BOARD

DBx_FSI

DBx_MCKI

 

 

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The Zone Audio Data Path is as follows: 

•  Output of the Zone Digital Receiver to the Audio FPGA 
•  A 2-channel stream is sent to the Analog section as ZONE_DAC_SDI. This stream is either the 

output of the Zone Digital Receiver or a 2-channel down-mix of the Main Audio content. 

There are three possible sources of master clock for the Zone Audio Path. The 22.5792mHz crystal 
oscillator that provides either a 44.1kHz or 88.2kHz sample rate, the 24.576 oscillator that provides either 
a 48kHz or 96kHz sample rate, or the master clock output of the Zone digital receiver. In practice, the unit 
runs off the crystal at 96kHz when the input is analog. When the input is digital, the master clock output of 
the digital receiver is used. Depending on the input selected, the appropriate master clock is routed from 
the DAR FPGA to the Audio FPGA. Here it drives a clock tree that divides down the master clock, which 
is 256 times the sample rate, 256FS, to create the other clock rates required. 

•  The Digital Receiver uses a word clock, FS, and bit clock, 64FS 
•  The Analog Board receives a 256FS Master Clock and a word clock, FS. These are used on the 

analog board to derive the audio clock signals required by the devices on that board. 

 

ZONE

DRCVR

24.576 MHZ

4896_MCK

ZONE_MCKO

ZONE

ANALOG

CLOCKS

ZONE_ANLG_FSI

ZONE_ANLG_MCKI

ZONE

DRCVR

CLOCK

ZONE_DRCVR_FSI

ZONE_DRCVR_SCKI

ZONE_DRCVR_MCKO

ZONE_DRCVR_SDO

TO

ANALOG

SECTION

TO

DIGITAL

RCVR

ZONE

DRCVR

ZONE_DRCVR_SDO

DSP BOARD

DOWNMIX

ANALOG

CONNECTORS

INPUT

MUX

DAC

OUTPUT

CONNECTOR

ZONE_SDO

OUTPUT

MUX

 

 

 

 

6-15

The MC-8 VCO board is an isolated Voltage-Controlled Oscillator module that forms part of an overall 
PLL for generating master clocks for digital audio in the MC-8 system. The board is housed in a shielded 
enclosure and mounts to the main board through a 5-pin in-line header J1, which carries control-voltage 
input, oscillator output, and 5-volt power and ground. The VCO assembly is soldered to the MC-8 main 
board, which incorporates the phase-detector and error amplifier to form the complete PLL. 

The analog section of the MC-8 encompasses all of the analog audio inputs and outputs, level controls 
and A/D and D/A converters. This section is located near the rear panel connections on the MC-8 Main 
Board. There are two separate signal paths: Main and Zone 2. Each of the eight analog stereo inputs or 
eight digital inputs can be routed to any of the two paths. The Main path digitizes the analog signal (if 
selected) and passes it to the DSP. Refer to the Main Audio Path 2-Channel Input block diagram in the 
next column. The DSP creates eight different output signals from the 2-channel input. D/A converter ICs 
convert each of the eight signals from the DSP to analog. The signals pass through level controls to their 
respective RCA connectors. A direct analog path is also provided which passes a 2-channel analog input 
signal directly to the Left and Right Front outputs via the level controls, bypassing the DSP and 
converters. 

The MC-8 Balanced version offers additional Balanced Main and Zone 2 analog outputs using XLR 
connectors. In this version, an internal 34-pin ribbon cable routes the post level control signals from the 
Analog board to the XLR board. The XLR board incorporates active balanced output drivers for each of 
the ten outputs. 

In addition, two 5.1-channel sources can be selected for the Main audio path. There are two possible 
methods of getting a 5.1-source into the box. Refer to the Main Audio Path 5.1-Channel Input block 
diagram above. 

1.  An S/PDIF signal may be encoded in Dolby Digital or DTS format and pass through a decoder that 

outputs the 5.1 channels. These channels are then passed along to the DSP.

 

2.  Two sets of three separate analog input pairs can be routed directly to the outputs, bypassing the 

DSP and converters. This mode is available for DVD-Audio and multi-channel SACD players with 5.1 
analog outputs. In the first case, Input 3 would pass to the Left and Right Front outputs; Input 4 would 
pass to the Center and Subwoofer outputs. Input 5 would pass to the Left and Right Side and Rear 
outputs. A duplicate set uses inputs 6, 7, and 8 in a similar manner. 

Any of the eight analog or eight digital audio inputs can be selected as the source for the Zone 2 Audio 
Path as shown in the Zone 2 Audio Paths block diagram below. An analog source can be passed directly 
to the analog outputs. Likewise, a digital source can be passed directly to the digital outputs and be 
routed to a D/A converter for the analog outputs. In addition, a 5.1 Dolby Digital or DTS encoded 5.1 
digital source may also be selected and passed through a decoder which will output a 2-channel downmix 
for the Zone 2 outputs. One S/PDIF RCA (coaxial) output port is available. 

 

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