DOWNLOAD JBL SDP-5 (serv.man7) Service Manual ↓ Size: 3.09 MB | Pages: 127 in PDF or view online for FREE

Model
SDP-5 (serv.man7)
Pages
127
Size
3.09 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
sdp-5-sm7.pdf
Date
PREV: JBL SDP-5 (serv.man6) EMC - CB Certificate

JBL SDP-5 (serv.man7) Service Manual ▷ View online

XC17S05XL
DATA
VCC
VPP
CE
CEO
OE
GND
CLK
XCS05-VQ100
21 4896_MCK
20
4_MHZ
19 A0
18 A1
9 A13
8 A14
7 A15
17 A2
16 A3
15 A4
14 A5
13 A6
10 A7
68
AUDIO_CCLK
74
CCLK
90 D0
91 D1
92 D2
93 D3
94 D4
95 D5
96 D6
97 D7
50
DONE
88
77
64
49
38
23
11
1
36
INIT
57
IO_AUDIO
72
IO_DIN 73
IO_DOUT
4
IO_SP0 5
IO_SP1
43
TEMP2
61 VIDEO_2
24
M0
22 M1
46
MAIN_DRCVR_ERR/STATUS
48 MAIN_DRCVR_MCK0
45
MAIN_DRDVRCS12/FCK
44
MAIN_MCKO
80
MEM_IO
26 NC2
27 PLL_MCKO
PLL_PUMP_UP 28
52 PROGRAM
83
RD/WR
69
SWRD_LEDWR/
62 VIDEO_3
TMS_AUDIO_DIN 55
100
89
75
63
51
37
25
12
71
VFD_EN
2 ZCLK
42
ZONE_DRCVR_CS12/FCK
41
ZONE_DRCVR_ERR/STATUS
ZONE_DRCVR_MCKO
39
35
ZONE_MCKO
56
AUDIO_FPGA
67
AUDIO_PROGRAM
81
CTRL2 82
CTRL3
31
DB0_CS 53
DB1_CS 78
DB2_CS
65
DSP_CS
70
FRONT_PANEL
58
IODX_EN
IODY_EN 59
85
IORD 84
IOWR
47
MAIN_DRCVR_RST
76
PIC_CONFIG
30
PLL_LOCK_DOWN
87 RESET
33 VIDEO_0
60 VIDEO_1
6
STATUS4
29
PLL_PUMP_DOWN
98 Z1ORQ
3 ZM1
40
ZONE_DRCVR_RST
99 ZRD
86
ZWAIT
34
TEMP1
66
DSP_IO 32
DB0_IO
79
DB2_IO
54
DB1_IO
GND
VCC
(TDO)
IO FPGA
(TDI)
(TCK)
(TMS)
+3.3VD
.1/25
10K
24.576MHZ
IN
VDD
OUT
GND
3.3V
+3.3VD
+5VD
DESCRIPTION
REV
CHECKER
DRAFTER
AUTH.
Q.C.
REVISIONS
1
SIZE
OF
3
2
A
B
C
D
1
2
3
4
5
6
7
8
4
5
6
7
8
A
B
C
D
NUMBER
CODE
Q.C.
ISSUED
DATE
APPROVALS
CONTRACT
NO.
SHEET
FILE NAME
B
DRAWN
CHECKED
TITLE
exicon
REV
3 OAK PARK
BEDFORD, MA  01730
+3.3VD
32KX8
70NS
43256
WE
OE
CE
VCC
GND
D7
D6
D5
D4
D3
D2
D1
D0
A9
A8
A7
A6
A5
A4
A3
A2
A14
A13
A12
A11
A10
A1
A0
EURO48-F
+3.3VD
EURO48-F
EURO48-F
+3.3VD
4.7K
*
10K
+3.3VD
10/14/04
CW
AT
9/27/04
9/27/04
AT
RWH
9/24/04
CW
9/12/02
KB
9/12/02
KB
9/12/02
RWH
8/30/02
3
CHANGED PER DCR 020827-00
KB
8/14/02
8/5/02
CBV
8/5/02
CW
2
CHANGED PER DCR 020731-00
RWH
8/1/02
KB
6/4/02
6/26/02
KB
6/24/02
CW
CHANGED PER DCR 020430-00
1
5/16/02
RWH
2/15/02
3/29/02
4/3/02
4/3/02
KAB
CW
CV
RWH
060-15259
NOTES
.
M1,M0 = 1,0 MASTER SERIAL MODE
M1,M0 = 1,1 SLAVE SERIAL MODE
1 M1,M0 HAVE WEAK PULLUPS
MEMORY BOARD CONNECTOR
SEE NOTES
1 & 2
TEST POINTS
2 JUMPER W2 TO GND TO USE CONFIGURATION ROM.
MEMORY CONN, RAM, I/O FPGA
4
4
SCHEM,MAIN BD,MC4/MC8
UPDATED FOR MC4  PER DCR 040922-00
15259-6
10-19-2004_8:58
2
2
23
R319
E30
AUDIO_4MHZ
[2/D1,4/C8]
ZONE_CS12/FCK
[9/B7]
[9/C7]
ZONE_ERR/STATUS
[9/B7]
ZONE_DRCVR_RST
[4/C1,4/B8]
ZONE_MCKO
[9/D7]
MAIN_CS12/FCK
MAIN_ERR/STATUS
[9/D7]
MAIN_DRCVR_RST
[9/C7]
[4/D1,4/C8]
MAIN_MCKO
PLL_LOCK_DOWN/
[10/B8]
[10/B8]
PLL_PUMP_DOWN/
PLL_PUMP_UP
[10/B8]
ZWAIT/
[1/C8,2/D1]
[2/D1,4/D8,5/C7,6/C7,7/C6,8/B6]
IO_RD/
IO_WR/
[2/D1,4/C8,5/B7,6/B7,7/B6,8/B6]
RD/WR
[2/D1,3/D7,3/C7,5/A7,6/A7,7/A6,8/A6,12/A7]
VFD_EN
[12/B7]
[12/B7]
SWRD_LEDWR/
[12/A7]
FRONT_PANEL/
AUDIO_FPGA/
[4/C8]
PIC_CONFIG
[3/C8]
IODX_EN/
[3/D7]
[3/C7]
IODY_EN/
DSP_CS/
[5/B4]
[6/B4]
DB0_CS/
DB1_CS/
[7/B4]
[8/B4]
DB2_CS/
CONTROL_2/
[3/D5]
[3/C5]
CONTROL_3/
[3/B8]
STATUS_4/
[1/B3]
IO_PROGRAM/
[1/B8]
BSY/RDY
4896_MCK
4896_MCK
ZD7
ZD5
ZD6
ZD7
ZD4
ZD0
ZD1
ZD2
ZD3
ZD6
ZD5
ZD4
ZD3
ZD2
ZD1
ZD0
ZD[7:0]
[1/D3,3/D7,5/A7,6/B6,7/A6,8/A6]
ZD0
ZD1
ZD2
ZD3
ZD7
ZD4
ZD5
ZD6
ZCLK
[1/D3,1/C1]
TEMP1
[12/C6]
R314
[12/D3]
SYNC_DETECT
VIDEO_2
[12/D3]
VIDEO_1
[12/D3]
VIDEO_0
[12/D3]
TEMP2
[12/C6]
IO_RST/
[1/B3,3/B8,4/C8]
ZM1/
[1/C3,1/C1]
ZRD/
[1/B5,1/C1]
ZIORQ/
[1/C3,1/C1]
R313
1
2
3
4
J33
AUDIO_4MHZ
ZONE_DRCVR_MCKO
IO_RD/
MAIN_DRCVR_MCKO
RD/WR
IO_WR/
ZWAIT/
4MHZ
RD/WR
4896
DSP_IO
[5/D7]
[1/B3]
IO_CCLK
[1/B3]
IO_DIN
W2
*
R318
E31
B1
B10
B11
B12
B13
B14
B15
B16
B2
B3
B4
B5
B6
B7
B8
B9
J48
C1
C10
C11
C12
C13
C14
C15
C16
C2
C3
C4
C5
C6
C7
C8
C9
J48
A1
A10
A11
A12
A13
A14
A15
A16
A2
A3
A4
A5
A6
A7
A8
A9
J48
27
22
20
28
14
19
18
17
16
15
13
12
11
24
25
3
4
5
6
7
8
1
26
2
23
21
9
10
U90
ZWAIT/
IO_WR/
IO_RD/
AUDIO_PROGRAM/
[4/D8]
[4/D4]
AUDIO_CCLK
AUDIO_DIN
[4/D4]
NC
NC
DB2_IO
[8/D6]
DB1_IO
[7/D6]
DB0_IO
[6/D7]
ZONE_DRCVR_MCKO
[2/D1,9/B4]
[2/D1,9/D4]
MAIN_DRCVR_MCKO
PLL_MCKO
[4/D1,10/B2]
[12/B7]
IO_DONE
NC
IO_AUDIO
[4/A4]
MEM_IO
[1/B3]
R325
56
1
4
3
2
U73
R326
C357
R320
R323
R324
R321
R388
R322
MAIN_DRCVR_MCKO
ZONE_DRCVR_MCKO
ZA5
ZA4
ZA3
ZA2
ZA1
ZA0
ZA13
ZA12
ZA11
ZA10
ZA9
ZA8
ZA7
ZA6
ZA5
ZA4
ZA3
ZA2
ZA1
ZA0
ZA14
ZA13
ZA7
ZA6
ZA5
ZA4
ZA3
ZA2
ZA1
ZA0
ZA15
[1/D4,4/D7,5/C7,6/C6,7/C6,8/C6,12/A6]
ZA12
ZA13
ZA14
ZA6
ZA7
ZA8
ZA9
ZA10
ZA11
ZA[15:0]
[3/B5]
BAT_VCC
SA_14
[1/C3]
[1/C3]
SRAM_WR/
[3/B5]
SRAM_EN/
[1/C3]
SRAM_RD/
[1/B3]
EPROM/
FLASH_RST/
[1/B3]
[1/B3]
FLASH_WR/
[1/B3]
FLASH0/
MEM_SPARE
[1/B3]
MEM_RD/
[1/B3]
RA21
RA22
RA20
RA19
RA15
RA16
RA17
RA18
RA[22:15]
[1/B3]
U72
*
U79
16C54
OS1
OS2
RA0
RA1
RA2
RA3
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
RTCC
VDD
VSS
MCLR
2.2/35
BAR35
2.2K
+5VD
470PF
MC34164
GND
IN
RESET
2N3906
47K
1N914
2N3904
2N3904
10K
2N3906
+5VD
100K
+5VD
1.00K
1%
+5VD
10K
4.7K
4.7K
+5VD
1K
3V
+
-
.1/25
74VHCT245
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
DIR
G
74VHCT541
A1
A2
A3
A4
A5
A6
A7
A8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
1G
2G
+3.3VD
+3.3VD
10K
220
220
YEL
YEL
YEL
GRN
YEL
220
220
220
220
CLR
CLK
8D
7D
6D
5D
4D
3D
2D
8Q
7Q
4Q
3Q
1Q
2Q
5Q
6Q
1D
74VHC273-3.3V
+5VD
DESCRIPTION
REV
CHECKER
DRAFTER
AUTH.
Q.C.
REVISIONS
1
SIZE
OF
3
2
A
B
C
D
1
2
3
4
5
6
7
8
4
5
6
7
8
A
B
C
D
NUMBER
CODE
Q.C.
ISSUED
DATE
APPROVALS
CONTRACT
NO.
SHEET
FILE NAME
B
DRAWN
CHECKED
TITLE
exicon
REV
3 OAK PARK
BEDFORD, MA  01730
74VHC04-5V
74VHC04-5V
220
GRN
220
74VHC04-5V
74VHC04-5V
74VHC04-5V
74VHC04-5V
74VHCT245
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
DIR
G
GRN
GRN
CLR
CLK
8D
7D
6D
5D
4D
3D
2D
8Q
7Q
4Q
3Q
1Q
2Q
5Q
6Q
1D
74VHC273-3.3V
1N914
+3.3VD
1K
1K
1K
10/14/04
CW
AT
9/27/04
9/27/04
AT
CW
9/12/02
KB
9/12/02
KB
9/12/02
RWH
8/30/02
3
CHANGED PER DCR 020827-00
KB
8/14/02
8/5/02
CBV
8/5/02
CW
2
CHANGED PER DCR 020731-00
RWH
8/1/02
KB
6/4/02
6/26/02
KB
6/24/02
CW
CHANGED PER DCR 020430-00
1
5/16/02
RWH
2/15/02
3/29/02
4/3/02
4/3/02
KAB
CW
CV
RESET / BATTERY BACKUP
+5V MONITOR
RWH
IR RECEIVER
.
SPARES
TIMER INT
060-15259
STATUS & CTL REGISTERS, IR RCVR
4
4
RWH
9/24/04
SCHEM,MAIN BD,MC4/MC8
UPDATED FOR MC4  PER DCR 040922-00
23
3
3
10-19-2004_8:58
15259-6
R432
R431
[2/C3]
CONTROL_2/
[2/C3]
CONTROL_3/
BAT_VCC
[2/D8]
PWR_RST/
100
R276
R269
100
100
R270
IODX6
IODX5
IODX4
IODX2
IODX1
IODX0
IODX3
IODX7
IODX[7:0]
[21/B6]
DB2_RST/
[8/B4]
[2/D1,2/D3,3/D7,5/A7,6/A7,7/A6,8/A6,12/A7]
RD/WR
[2/C3]
IODY_EN/
RD/WR
[2/D1,2/D3,3/C7,5/A7,6/A7,7/A6,8/A6,12/A7]
IODX_EN/
[2/C3]
[1/D3,2/D6,5/A7,6/B6,7/A6,8/A6]
ZD[7:0]
ZD1
ZD0
ZD0
ZD1
ZD2
ZD3
ZD4
ZD5
ZD6
ZD7
ZD7
ZD6
ZD5
ZD4
ZD3
ZD2
DSP_RST/
[5/A7]
R409
D46
1
11
18
17
14
13
8
7
4
19
16
9
6
2
5
12
15
3
U94
D53
D55
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
1
19
U95
NC
13
12
U88
8
9
U88
1
2
U88
6
5
U88
R427
D59
R425
10
11
U88
4
3
U88
NC
3
15
12
5
2
6
9
16
19
4
7
8
13
14
17
18
11
1
U93
R428 R429
R426
R424
D56
D57
D58
D54
1
2
3
4
5
6
7
8
9
J47
D52
R423
R422
NC
NC
NC
R408
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
1
19
U92
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
1
19
U61
[6/A7]
DB0_RST/
DB1_RST/
[7/B4]
REMOTE_PWREN1/
[11/D7]
[11/C7]
REMOTE_PWREN0/
[12/D8]
FAN_ON
PIC_RST/
[3/C8]
C396
BAT1
R437
R433
R436
R435
R439
R440
Q6
R430
Q9
Q7
D60
R438
Q8
1
2
4
U98
C414
R434
D61
C415
PWR_RST/
[1/B8]
[2/C8]
SRAM_EN/
STATUS_4/
[2/C3]
STATUS_4/
1MHZ
[4/B1,4/C4]
PIC_RST/
[3/D3]
PIC_CONFIG
[2/C3]
NC
[12/B2]
IR_DATA
IODY7
IODY6
IODY5
IODY4
IODY3
IODY2
IODY1
IODY0
IODY0
IODY1
IODY2
IODY3
IODY4
IODY5
IODY6
IODY7
IODY0
IODY1
IODY2
IODY3
IODY4
IODY5
IODY7
IODY6
IODY[7:0]
[4/D7,12/A6]
IODY7
IODY6
IODY5
IODY4
IODY3
IODY2
IODY1
IODY0
[1/B3,2/C5,4/C8]
IO_RST/
NC
IR_ACK_PIC
[12/A7]
R272
100
100
R271
R275
100
R274
100
100
R273
V_BAT
16
15
17
18
1
2
6
7
8
9
10
11
12
13
3
14
5
4
U89
XCS20XL-4PQ208
DSP_AUDIO2
136
DB0_AUDIO_SP0
31
102 DB1_AUDIO2
159 DB2_AUDIO_SP0
1MHZ 196
55 4_MHZ
194 A0
193 A1
191 A2
190 A3
189 A4
A5
188
187 A6
155
CCLK
56 COAX1
57 COAX2
58 COAX3
59 COAX4
186 D0
185 D1
178 D6
177 D7
16
DB0_AUDIO0 17
DB0_AUDIO1
30 DB0_AUDIO10
20
DB0_AUDIO3
DB0_AUDIO4 21
DB0_AUDIO5 22
23 DB0_AUDIO6
24 DB0_AUDIO7
27 DB0_AUDIO8
29 DB0_AUDIO9
157
DB1_AUDIO0 152
DB1_AUDIO1
141 DB1_AUDIO10
151
DB1_AUDIO3 150
DB1_AUDIO4 149
DB1_AUDIO5
148 DB1_AUDIO6
147 DB1_AUDIO7
146 DB1_AUDIO8
142 DB1_AUDIO9
174
DB2_AUDIO0 172
DB2_AUDIO1
162 DB2_AUDIO9
171
DB2_AUDIO3 169
DB2_AUDIO4
DB2_AUDIO_4MHZ 163
DB2_AUDIO2
160
DB2_AUDIO6
167
DB2_AUDIO7
166
164 DB2_AUDIO8
DONE 104
DSP_AUDIO0 138
137
DSP_AUDIO1
125 DSP_AUDIO10
135
DSP_AUDIO3 134
DSP_AUDIO4 133
DSP_AUDIO5
132 DSP_AUDIO6
129 DSP_AUDIO7
DSP_AUDIO8
128
126 DSP_AUDIO9
1 13
131 143 158 170 182 195
25 38 51 66 79 91 103 118
201
IO_AUDIO
IO_DIN 153
IO_DOUT 154
M1 50
74 MAIN_ADC_SDO
70
MAIN_AD_FSI
72
MAIN_AD_MCKI
73
MAIN_AD_SCKI
6 MAIN_C0/
7 MAIN_CA
8 MAIN_CB
9 MAIN_CC
10 MAIN_CD
11 MAIN_CE
107
MAIN_DAC0_SDI 108
MAIN_DAC1_SDI 109
MAIN_DAC2_SDI 110
MAIN_DAC3_SDI
98
MAIN_DAC_CDATA
99
MAIN_DAC_FSI
101
MAIN_DAC_MCKI
100
MAIN_DAC_SCKI
14
MAIN_DRCVR_NRZI
5 MAIN_DRCVR_SDO
15 MAIN_ERF
76
MAIN_IN_VC_CLK 80
MAIN_IN_VC_DATA
2 MAIN_MCKO
93
MAIN_OUT_VC_CLK 94
MAIN_OUT_VC_DATA
200
MEM_AUDIO
12 39 54 65 92 111
144 165 202 203
OPTO1
60
OPTO2
61
OPTO3
62
OPTO4
63
32 SP0
34 SP1
175 SP2
176 SP3
113
TCK_ZONE_OUT_VC_CLK
97
TDI_MAIN_DAC_CCLK
18 26
140 156 173 183 192 208
33 53 71 78 86 105 121 130
68
VIDEO_CCLK 69
VIDEO_CDATA
45 ZONE_C0/
ZONE_CA
44
43 ZONE_CB
42 ZONE_CC
41 ZONE_CD
40 ZONE_CE
117
ZONE_DAC_CS
ZONE_DAC_FSI 48
ZONE_DAC_MCKI 119
ZONE_DAC_SCKI 47
123
ZONE_DAC_SDI
37
ZONE_DRCVR_NRZI
120
ZONE_DRCVR_SCKI
46 ZONE_DRCVR_SDO
ZONE_ERF
36
49 ZONE_MCKO
35
ZONE_NRZO
114
ZONE_OUT_VC_DATA
81
ANLG_0 82
ANLG_1 83
ANLG_3 84
ANLG_4 85
ANLG_6
205 CS
88
CTR_SUB_VC_CS
95
FRONT_DAC_CS
87
FRONT_VC_CS
IO_INIT 77
96
MAIN_DAC_CS
75
MAIN_IN_VC_CS
OSD 64
106 PROG
206 RD
90
REAR_VC_CS
204 RESET
89
SIDE_VC_CS
67
VIDEO_REG
207 WR
199
ZINT0 198
ZINT1 197
ZINT2
ZONE_OUT_VC_CS 112
184 D2
181 D3
179 D5
180 D4
3
MAIN_DRCVR_FSI 4
MAIN_DRCVR_SCKI
122
ZONE_DRCVR_FSI
DB2_AUDIO5 168
DB2_AUDIO10
161
DB1_AUDIO_4MHZ 145
DB1_AUDIO_SP0
139
19 DB0_AUDIO2
28
DB0_AUDIO_4MHZ
127
DSP_AUDIO_4MHZ
124 DSP_AUDIO_SP0
M0 52
116
ZONE_DAC_CDATA
115
ZONE_DAC_CCLK
AUDIO FPGA
GND
NC
NC
VCC
+3.3VD
*
DESCRIPTION
REV
CHECKER
DRAFTER
AUTH.
Q.C.
REVISIONS
1
SIZE
OF
3
2
A
B
C
D
1
2
3
4
5
6
7
8
4
5
6
7
8
A
B
C
D
NUMBER
CODE
Q.C.
ISSUED
DATE
APPROVALS
CONTRACT
NO.
SHEET
FILE NAME
B
DRAWN
CHECKED
TITLE
exicon
REV
3 OAK PARK
BEDFORD, MA  01730
XC17S20
DATA
VCC
VPP
CE
CEO
OE
GND
CLK
+3.3VD
4.7K
+3.3VD
74VHC04-3.3V
74VHC04-3.3V
74VHC04-3.3V
74VHC04-3.3V
74VHC04-3.3V
74VHC04-3.3V
10K
+3.3VD +3.3VD
NOTES
10/14/04
CW
AT
9/27/04
9/27/04
AT
4
RWH
9/24/04
CW
9/12/02
KB
9/12/02
KB
9/12/02
RWH
8/30/02
3
CHANGED PER DCR 020827-00
KB
8/14/02
8/5/02
CBV
8/5/02
CW
2
CHANGED PER DCR 020731-00
RWH
8/1/02
KB
6/4/02
6/26/02
KB
6/24/02
CW
SPARES
CHANGED PER DCR 020430-00
1
5/16/02
RWH
2/15/02
3/29/02
4/3/02
4/3/02
KAB
CW
CV
RWH
060-15259
1 & 2
M1,M0 = 1,0 MASTER SERIAL MODE
M1,M0 = 1,1 SLAVE SERIAL MODE
.
1 M1,M0 HAVE WEAK PULLUPS
SEE NOTES
MAIN PATH
ZONE PATH
VIDEO CONTROL
AUDIO FPGA
PIC CLOCK
TEST POINTS
2 JUMPER W3 TO GND TO USE CONFIGURATION ROM.
4
SCHEM,MAIN BD,MC4/MC8
UPDATED FOR MC4  PER DCR 040922-00
23
10-19-2004_8:59
4
4
15259-6
R367
56
§
R339
33
§
33
R357
§
R358
33
§
33
R363
§
R359
33
§
33
R364
§
33
R360
§
33
R332
§
R340
33
§
33
R333
§
R341
33
§
33
R356
§
R279
100
§
R366
56
§
R368
33
§
33
R328
§
R335
33
§
ZONE_NRZO
[9/A7]
1K
R280
§
100
R281
§
100
R282
§
1K
R284
§
R285
100
§
R283
100
§
DB2_AUDIO8
DB2_AUDIO[10:0]
[4/A4,8/D6]
DB2_AUDIO10
DB2_AUDIO9
DB2_AUDIO7
DB2_AUDIO6
DB2_AUDIO2
DB1_AUDIO9
DB1_AUDIO[10:0]
[4/B4,7/D5]
DB1_AUDIO10
DB1_AUDIO8
DB1_AUDIO7
DB1_AUDIO6
DB1_AUDIO2
[5/C7]
DSP_AUDIO_4MHZ
[4/C1,16/C8]
ZONE_DAC_SDI
[4/A7,8/D6]
DB2_AUDIO[10:0]
DB2_AUDIO5
DB2_AUDIO4
DB2_AUDIO3
DB2_AUDIO1
DB2_AUDIO0
[4/B7,7/D5]
DB1_AUDIO[10:0]
DB1_AUDIO5
DB1_AUDIO4
DB1_AUDIO3
DB1_AUDIO1
DB1_AUDIO0
DB0_AUDIO[10:0]
[4/B7,6/D6]
DB0_AUDIO5
DB0_AUDIO4
DB0_AUDIO3
DB0_AUDIO1
DB0_AUDIO0
[4/B7,5/D6]
DSP_AUDIO[10:0]
DSP_AUDIO0
DSP_AUDIO1
DSP_AUDIO3
DSP_AUDIO4
DSP_AUDIO5
DB1_AUDIO_SP0
[7/C6]
DB0_AUDIO_SP0
[6/C7]
DSP_AUDIO_SP0
[5/C7]
DB0_AUDIO[10:0]
[4/B4,6/D6]
DB0_AUDIO10
DB0_AUDIO9
DB0_AUDIO8
DB0_AUDIO7
DB0_AUDIO6
DB0_AUDIO2
ZONE_ERF
[9/B4]
[2/C3]
AUDIO_PROGRAM/
IODY[7:0]
[3/D6,12/A6]
IODY7
IODY0
IODY1
IODY3
IODY4
IODY5
IODY6
IODY2
[1/D4,2/D8,5/C7,6/C6,7/C6,8/C6,12/A6]
ZA[15:0]
ZA6
ZA5
ZA4
ZA0
ZA1
ZA3
ZA2
IO_RD/
[2/D1,2/D3,5/C7,6/C7,7/C6,8/B6]
IO_WR/
[2/D1,2/D3,5/B7,6/B7,7/B6,8/B6]
AUDIO_FPGA/
[2/C3]
[1/B3,2/C5,3/B8]
IO_RST/
AUDIO_4MHZ
[2/D1,2/B3]
[12/C3]
OPTO[4:1]
OPTO1
OPTO2
OPTO4
OPTO3
COAX[4:1]
[12/D3]
COAX1
COAX4
COAX3
COAX2
MAIN_MCKO
[2/B3,4/D1]
MAIN_ADC_SDO
[15/B2]
MAIN_DRCVR_SDO
[4/D1,9/D4]
MAIN_C0/
[9/D4]
MAIN_CA
[9/D4]
[9/D4]
MAIN_CB
MAIN_CC
[9/D4]
[9/D4]
MAIN_CD
MAIN_CE
[9/C4]
[9/C4]
MAIN_ERF
ZONE_CE
[9/B4]
[9/B4]
ZONE_CD
ZONE_CC
[9/B4]
[9/B4]
ZONE_CB
ZONE_CA
[9/B4]
ZONE_C0/
[9/B4]
[2/B3,4/C1]
ZONE_MCKO
[4/C1,9/B4]
ZONE_DRCVR_SDO
ANLG_REG0_CS/
[21/D6]
ANLG_REG1_CS/
[21/C6]
ANLG_REG3_CS/
[21/B6]
ANLG_REG4_CS/
[21/B6]
ANLG_REG6_CS/
[21/A6]
MAININ_VC_CS/
[15/B8]
MAININ_VC_CLK
[15/B8]
MAININ_VC_DATA
[15/B8]
FRONT_VC_CS/
[17/A8]
CENTER_VC_CS/
[18/A8]
SIDE_VC_CS/
[19/A8]
REAR_VC_CS/
[20/A8]
MAINOUT_VC_CLK
[17/B8,18/B8,19/B8,20/B8]
MAINOUT_VC_DATA
[17/A8,18/B8,19/B8,20/A8]
[17/C8]
FRONT_DAC_CS/
[18/C8,19/C8,20/C8]
MAIN_DAC_CS/
MAIN_DAC_CCLK
[17/C8,18/C8,19/C8,20/C8]
MAIN_DAC_CDATA
[17/C8,18/C8,19/C8,20/C8]
ZONE_VC_CLK
[16/B8]
ZONE_VC_DATA
[16/B8]
ZONE_DAC_CCLK
[16/C8]
ZONE_DAC_CDATA
[16/C8]
ZONE_DAC_CS/
[16/C8]
[4/C1,17/C8]
FRONT_DAC_SDI
[4/C1,18/C8]
CENTER_DAC_SDI
SIDE_DAC_SDI
[4/C1,19/C8]
[4/C1,20/C8]
REAR_DAC_SDI
100
R286
R287
100
100
R288
R289
100
R342
[4/C1,19/D8,20/D8]
MAIN_DAC_SCKI1/
SIDE_DAC_MCKI
[19/D8]
R266
56
R268
56
R265
56
R267
56
R345
56
R346
56
R347
56
R348
56
R352
100
100
R353
R354
100
R355
100
R344
56
R349
56
R350
56
MAIN_ADC_MCKI/
[15/B2]
[9/D7]
MAIN_DRCVR_NRZI
R351
56
MAIN_DRCVR_SCKI
[4/D1,9/D7]
MAIN_ADC_FSI/
[15/B2]
R377
33
33
R361
13
12
U58
10
11
U58
9
8
U58
2
1
U58
3
4
U58
6
5
U58
MEM_AUDIO
[1/B3]
REAR_DAC_MCKI
[20/D8]
FRONT_DAC_MCKI
[17/D8]
[4/C1,17/C8,18/C8]
MAIN_DAC_FSI0/
[4/C1,19/C8,20/C8]
MAIN_DAC_FSI1/
[4/C1,17/D8,18/D8]
MAIN_DAC_SCKI0/
MAIN_DAC_SCKI/
PLL_MCKO
ZDAC_SDI
MAIN_DAC_MCKI/
100
R300
R301
100
100
R302
R303
100
100
R304
VIDEO_DATA
[4/B1,12/D5]
[4/C1,12/D5]
VIDEO_REG/
OSD/
[4/C1,12/D5]
1K
R290
100
R291
100
R292
R305
1K
R373
33
MAIN_ADC_SCKI/
[15/B2]
ZONE_DAC_FSI/
[4/C1,16/C8]
[4/C1,16/C8]
ZONE_DAC_SCKI/
MDAC_SCKI0
MDAC_SCKI1
MAIN_DAC_SCKI1/
MAIN_DAC_SCKI0/
MAIN_DAC_FSI1/
ZDAC_FSI
ZDAC_SCKI
ZDAC_MCKI
PLL_OUT
R327
AUDIO_CCLK
[2/C3]
E33
AUDIO_DIN
[2/C3]
W3
*
AUDIO_DONE
[12/C7]
NC
VIDEO_SCLK
[4/B1,12/D5]
[3/C8,4/B1]
1MHZ
MAIN_DRCVR_FSI
[4/D1,9/D7]
[9/B7]
ZONE_DRCVR_NRZI
[4/C1,9/B7]
ZONE_DRCVR_SCKI
[4/C1,9/B7]
ZONE_DRCVR_FSI
ZONE_DRCVR_SDO
MDRX_SDO
MAIN_DRCVR_SDO
2
1
5
8
7
4
6
3
*
U78
ZDRX_SDO
MMCK
MAIN_MCKO
ZDRX_FSI
FPGA_PROG/
ZONE_DRCVR_SCKI
ZDRX_SCKI
MDRX_SCKI
MDRX_FSI
MAIN_DRCVR_SCKI
ZONE_DRCVR_FSI
MAIN_DRCVR_FSI
ZMCK
ZONE_MCKO
NC NC NC NC NC
NC NC NC NC
NC
VSCLK
VDATA
VREG
OSD
OSD/
VIDEO_REG/
VIDEO_DATA
VIDEO_SCLK
IO_AUDIO
[2/A3]
1
2
3
4
J39
R343
R365
R362
1MHZ
1MHZ
MAIN_DAC_FSI/
MDAC_FCKI
MAIN_DAC_SCKI/
MDAC_FSI
MDAC_MCKI
MAIN_DAC_MCKI/
FRONT_DAC_SDI
FDAC_SDI
CENTER_DAC_SDI
SDAC_SDI
SIDE_DAC_SDI
CDAC_SDI
RDAC_SDI
REAR_DAC_SDI
ZONE_DAC_FSI/
ZONE_DAC_SCKI/
ZONE_DAC_MCKI
ZONE_DAC_SDI
MAIN_DAC_FSI0/
MDAC_FSI1
MDAC_FSI0
33
R376
[1/C1,1/C8]
ZINT0/
[1/C1,1/C8]
ZINT1/
[1/C1,1/C8]
ZINT2/
R307
100
100
R306
100
R299
R298
100
100
R297
R296
100
100
R295
1K
R294
100
R293
R374
33
33
R372
33
R375
33
R371
33
R370
R369
33
33
R336
R329
33
R330
33
R331
33
R338
33
33
R337
NC
NC
NC
MAIN_DAC_FSI/
CENTER_DAC_MCKI
[18/D8]
ZONE_VC_CS/
[16/A8]
DSP_AUDIO[10:0]
[4/B4,5/D6]
DSP_AUDIO2
DSP_AUDIO6
DSP_AUDIO7
DSP_AUDIO8
DSP_AUDIO9
DSP_AUDIO10
[8/C6]
DB2_AUDIO_SP0
DB0_AUDIO_4MHZ
[6/C7]
[7/C6]
DB1_AUDIO_4MHZ
DB2_AUDIO_4MHZ
[8/C6]
[4/C1,16/D8]
ZONE_DAC_MCKI
R334
56
§
U87
+3.3VD +5VD
74VHCT245
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
DIR
G
A4
A3
A2
A1
Y1
Y2
Y4
Y3
G
74VHCT244
A4
A3
A2
A1
Y1
Y2
Y4
Y3
G
74VHCT244
DESCRIPTION
REV
CHECKER
DRAFTER
AUTH.
Q.C.
REVISIONS
1
SIZE
OF
3
2
A
B
C
D
1
2
3
4
5
6
7
8
4
5
6
7
8
A
B
C
D
NUMBER
CODE
Q.C.
ISSUED
DATE
APPROVALS
CONTRACT
NO.
SHEET
FILE NAME
B
DRAWN
CHECKED
TITLE
exicon
REV
3 OAK PARK
BEDFORD, MA  01730
EURO64-F
A4
A3
A2
A1
Y1
Y2
Y4
Y3
G
74VHCT244
A4
A3
A2
A1
Y1
Y2
Y4
Y3
G
74VHCT244
10/14/04
CW
AT
9/27/04
9/27/04
AT
4
RWH
9/24/04
CW
9/12/02
KB
9/12/02
KB
9/12/02
RWH
8/30/02
3
CHANGED PER DCR 020827-00
KB
8/14/02
8/5/02
CBV
8/5/02
CW
2
CHANGED PER DCR 020731-00
RWH
8/1/02
KB
6/4/02
6/26/02
KB
6/24/02
CW
CHANGED PER DCR 020430-00
1
5/16/02
RWH
2/15/02
3/29/02
4/3/02
4/3/02
KAB
CW
CV
RWH
060-15259
.
DSP BOARD CONNECTOR
4
SCHEM,MAIN BD,MC4/MC8
UPDATED FOR MC4  PER DCR 040922-00
23
10-19-2004_8:58
5
15259-6
5
[4/B8]
DSP_AUDIO_SP0
DSP_AUDIO_SP0
[4/B4]
DSP_AUDIO_4MHZ
DSP_RST/
[3/D3]
DSP_RST/
DSP_CS/
[2/C3]
DSP_CS/
DSP_CS/
RD/WR
[2/D1,2/D3,3/D7,3/C7,6/A7,7/A6,8/A6,12/A7]
[1/D3,2/D6,3/D7,6/B6,7/A6,8/A6]
ZD[7:0]
ZD7
ZD0
ZD1
ZD6
ZD5
ZD4
ZD3
ZD2
DSP_IO
[2/B3]
[4/B4,4/B7]
DSP_AUDIO[10:0]
DSP_AUDIO9
DSP_AUDIO10
DSP_AUDIO8
DSP_AUDIO7
DSP_AUDIO6
DSP_AUDIO5
DSP_AUDIO4
DSP_AUDIO3
DSP_AUDIO2
DSP_AUDIO1
DSP_AUDIO0
ZDSP_RD/
ZDSP_RD/
ZDSP_D[7:0]
ZDSP_D0
ZDSP_D7
ZDSP_D6
ZDSP_D5
ZDSP_D4
ZDSP_D3
ZDSP_D2
ZDSP_D1
ZDSP_D0
ZDSP_D1
ZDSP_D2
ZDSP_D3
ZDSP_D4
ZDSP_D5
ZDSP_D6
ZDSP_D7
[2/D1,2/D3,4/C8,6/B7,7/B6,8/B6]
IO_WR/
E29
[1/D4,2/D8,4/D7,6/C6,7/C6,8/C6,12/A6]
ZA[15:0]
ZA6
ZA7
ZA9
ZA11
ZA13
ZA12
ZA10
ZA8
ZA2
ZA0
ZA1
ZA3
ZA5
ZA4
17
15
13
11
9
7
3
5
19
U81
1
14
12
16
18
2
4
6
8
U81
C32
C27
C28
C29
C30
C31
C25
C26
C24
C23
C22
C21
C19
C20
C18
C17
C16
C15
C13
C14
C12
C11
C10
C9
C4
C7
C8
C6
C5
C3
C2
A1
A2
A5
A6
A8
A7
A9
A10
A11
A12
A14
A13
A15
A16
A17
A18
A19
A21
A22
A23
A24
A26
A25
A31
A30
A29
A28
A27
A32
A3
A4
C1
A20
J38
17
15
13
11
9
7
3
5
19
U82
8
6
4
2
18
16
12
14
1
U82
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
1
19
U80
ZDSP_WR/
ZDSP_WR/
[2/D1,2/D3,4/D8,6/C7,7/C6,8/B6]
IO_RD/
DSP_A9
DSP_A11
DSP_A12
DSP_A13
DSP_A10
DSP_A0
DSP_A1
DSP_A2
DSP_A3
DSP_A4
DSP_A5
DSP_A6
DSP_A7
DSP_A8
DSP_A2
DSP_A13
DSP_A11
DSP_A9
DSP_A7
DSP_A12
DSP_A10
DSP_A8
DSP_A6
DSP_A4
DSP_A0
DSP_A1
DSP_A3
DSP_A5
DSP_A[13:0]
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