JBL ES250PW (serv.man2) Service Manual ▷ View online
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT165
FEATURES
•
Asynchronous 8-bit parallel load
•
Synchronous serial input
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT165 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT165 are 8-bit parallel-load or serial-in shift
registers with complementary serial outputs (Q
registers with complementary serial outputs (Q
7
and
Q
7
) available from the last stage. When the parallel load
(PL) input is LOW, parallel data from the D
0
to
D
7
inputs are loaded into the register asynchronously.
When PL is HIGH, data enters the register serially at the
D
D
s
input and shifts one place to the right
(Q
0
→
Q
1
→
Q
2
, etc.) with each positive-going clock
transition. This feature allows parallel-to-serial converter
expansion by tying the Q
expansion by tying the Q
7
output to the D
S
input of the
succeeding stage.
The clock input is a gated-OR structure which allows one
input to be used as an active LOW clock enable (CE) input.
The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The
LOW-to-HIGH transition of input CE should only take
place while CP HIGH for predictable operation. Either the
CP or the CE should be HIGH before the
LOW-to-HIGH transition of PL to prevent shifting the data
when PL is activated.
input to be used as an active LOW clock enable (CE) input.
The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The
LOW-to-HIGH transition of input CE should only take
place while CP HIGH for predictable operation. Either the
CP or the CE should be HIGH before the
LOW-to-HIGH transition of PL to prevent shifting the data
when PL is activated.
APPLICATIONS
•
Parallel-to-serial data conversion
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µ
W):
P
D
= C
PD
×
V
CC
2
×
f
i
+ ∑
(C
L
×
V
CC
2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC
2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay
CP to Q
7,
Q
7
PL to Q
7,
Q
7
D
7
to Q
7,
Q
7
C
L
= 15 pF; V
CC
= 5 V
16
15
11
15
11
14
17
11
17
11
ns
ns
ns
ns
ns
f
max
maximum clock frequency
56
48
MHz
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation capacitance per
package
package
notes 1 and 2
35
35
pF
ES250PW
32
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT165
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1
PL
asynchronous parallel load input (active LOW)
7
Q
7
complementary output from the last stage
9
Q
7
serial output from the last stage
2
CP
clock input (LOW-to-HIGH edge-triggered)
8
GND
ground (0 V)
10
D
s
serial data input
11, 12, 13, 14, 3, 4, 5, 6
D
0
to D
7
parallel data inputs
15
CE
clock enable input (active LOW)
16
V
CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
ES250PW
33
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT165
FUNCTION TABLE
Note
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the
LOW-to-HIGH clock transition
X = don’t care
↑
= LOW-to-HIGH clock transition
OPERATING MODES
INPUTS
Q
n
REGISTERS
OUTPUTS
PL
CE
CP
D
S
D
0
-D
7
Q
0
Q
1
-Q
6
Q
7
Q
7
parallel load
L
L
L
X
X
X
X
X
X
X
X
X
L
H
H
L
H
H
L - L
H - H
L
H
H
H
L
L
serial shift
H
H
H
L
L
L
↑
↑
l
h
h
X
X
X
L
H
H
q
0
-q
5
q
0
-q
5
q
6
q
6
q
6
q
6
hold “do nothing”
H
H
X
X
X
q
0
q
1
-q
6
q
7
q
7
Fig.4 Functional diagram.
Fig.5 Logic diagram.
ES250PW
34
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Cirrus Logic reserves the right to modify this product without notice.
1
Cirrus Logic, Inc. 2000
(All Rights Reserved)
CS4340
24-Bit, 96 kHz Stereo DAC for Audio
Features
l
Complete Stereo DAC System: Interpolation,
D/A, Output Analog Filtering
D/A, Output Analog Filtering
l
101 dB Dynamic Range
l
91 dB THD+N
l
Low Clock Jitter Sensitivity
l
+3 V to +5 V Power Supply
l
Filtered Line Level Outputs
l
On-Chip Digital De-emphasis for 32, 44.1,
and 48 kHz
and 48 kHz
l
30 mW with 3 V supply
l
Popguard
®
Technology for Control of Clicks
and Pops
Description
The CS4340 is a complete stereo digital-to-analog sys-
tem including digital interpolation, fourth-order delta-
sigma digital-to-analog conversion, digital de-emphasis
and switched capacitor analog filtering. The advantages
of this architecture include: ideal differential linearity, no
distortion mechanisms due to resistor matching errors,
no linearity drift over time and temperature and a high
tolerance to clock jitter.
tem including digital interpolation, fourth-order delta-
sigma digital-to-analog conversion, digital de-emphasis
and switched capacitor analog filtering. The advantages
of this architecture include: ideal differential linearity, no
distortion mechanisms due to resistor matching errors,
no linearity drift over time and temperature and a high
tolerance to clock jitter.
The CS4340 accepts data at audio sample rates from
2 kHz to 100 kHz, consumes very little power, and oper-
ates over a wide power supply range. The features of the
CS4340 are ideal for DVD players, CD players, set-top
box and automotive systems.
2 kHz to 100 kHz, consumes very little power, and oper-
ates over a wide power supply range. The features of the
CS4340 are ideal for DVD players, CD players, set-top
box and automotive systems.
ORDERING INFORMATION
CS4340-KS
16-pin SOIC, -10 to 70 °C
CS4340-BS
16-pin SOIC, -40 to 85 °C
CDB4340
Evaluation Board
I
∆Σ
DAC
Analog Filter
Serial
Input
Interface
Interpolation
Filter
Analog Filter
MUTEC
AOUTL
AOUTR
RST
LRCK
SDATA
MCLK
∆Σ
External
Mute Control
SCLK/DEM1
DAC
Interpolation
Filter
De-emphasis
DEM0
DIF0 DIF1
NOV ‘00
DS297PP3
ES250PW
35
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