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Six 24-bit D/A, two 24-bit A/D Converters

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110 dB DAC / 114 dB ADC Dynamic Range

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-100 dB THD+N

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System Sampling Rates up to 192 kHz

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S/PDIF Receiver Compatible with EIAJ 
CP1201 and IEC-60958

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Recovered S/PDIF Clock or System Clock 
Selection

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8:2 S/PDIF Input MUX

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ADC High-Pass Filter for DC Offset Calibration

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Expandable ADC Channels and One-Line 
Mode Support

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Digital Output Volume Control with Soft Ramp

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Digital +/-15 dB Input Gain Adjust for ADC

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Differential Analog Architecture

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Supports Logic Levels between 1.8 V and 5 V

The CS42516 codec provides two analog-to-digital and
six digital-to-analog delta-sigma converters, as well as
an integrated S/PDIF receiver.

The CS42516 integrated S/PDIF receiver supports up
to eight inputs, clock recovery circuitry and format auto-
detection. The internal stereo ADC is capable of inde-
pendent channel gain control for single-ended or
differential analog inputs. All six channels of DAC pro-
vide digital volume control and differential analog
outputs. The general-purpose outputs may be driven
high or low, or mapped to a variety of DAC mute con-
trols or ADC overflow indicators.

The CS42516 is ideal for audio systems requiring wide
dynamic range, negligible distortion and low noise, such
as A/V receivers, DVD receivers, digital speaker and
automotive audio systems.

The CS42516 is available in a 64-pin LQFP package in
both Commercial (-10° to 70° C) and Automotive 
(-40° to 85° C) grades. The CDB42518 Customer Dem-
onstration board is also available for device evaluation.
Refer to 

“Ordering Information” on page 89

.

            

    

RST

RXP0

RXP1/GPO1

AD0/CS

SCL/CCLK

SDA/CDOUT

AD1/CDIN

VLC

AOUTA1+
AOUTA1-

AOUTB1+

AOUTA3+
AOUTA3-

AOUTA2-

AOUTB2-

AOUTA2+

AOUTB2+

AOUTB1-

AOUTB3+
AOUTB3-

AINL+
AINL-

AINR+

AINR-

FILT+

REFGND

VQ

Ref

ADC#1

ADC#2

Digital Filter

Digital Filter

Gain & Clip

Gain & Clip

CX_SCLK

CX_LRCK

CX_SDIN3

CX_SDIN2

CX_SDIN1

DGND VD

LPFLT

TXP

INT

Rx

Clock/Data

Recovery

S/PDIF 

Decoder

Control 

Port

DAC#1

DAC#2

DAC#3

DAC#4

DAC#5

DAC#6

D

igi

ta

l Filte

r

V

ol

ume

 C

ontr

o

l

DGND

RXP2/GPO2
RXP3/GPO3
RXP4/GPO4
RXP5/GPO5
RXP6/GPO6
RXP7/GPO7

VD

MUTEC

GPO

An

a

log

 F

ilt

er

VARX

AGND

AGND

VA

CODEC 

Serial 

Port

CX_SDOUT

ADCIN1
ADCIN2

VLS

SAI_LRCK
SAI_SCLK
SAI_SDOUT

OMCK

RMCK

Serial 
Audio 

Interface  

Port

ADC 

Serial 

Data

Internal MCLK

Mult/Div

DEM

C&U Bit

Data Buffer

Format 

Detector

MUTE

19

                  

CX_SDIN1
CX_SDIN2
CX_SDIN3

1

64
63

Codec Serial Audio Data Input (Input) - Input for two’s complement serial audio data. 

CX_SCLK

2

CODEC Serial Clock (Input/Output) - Serial clock for the CODEC serial audio interface.

CX_LRCK

3

CODEC Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on 
the CODEC serial audio data line.

VD

4

51

Digital Power (Input) - Positive power supply for the digital section.

DGND

5

52

Digital Ground (Input) - Ground reference. Should be connected to digital ground.

VLC

6

Control Port Power (Input) - Determines the required signal level for the control port.

SCL/CCLK

7

Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external pull-up 
resistor to the logic interface voltage in I²C mode as shown in the Typical Connection Diagram.

SDA/CDOUT

8

Serial Control Data (Input/Output) - SDA is a data I/O line in I²C mode and requires an external pull-up 
resistor to the logic interface voltage, as shown in the Typical Connection Diagram. CDOUT is the output 
data line for the control port interface in SPI mode.

AD1/CDIN

9

Address Bit 1 (I²C)/Serial Control Data (SPI) (Input) - AD1 is a chip address pin in I²C mode; CDIN is 
the input data line for the control port interface in SPI mode.

AD0/CS

10

Address Bit 0 (I²C)/Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C mode; CS 
is the chip select signal in SPI mode.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17 18 19 20 21

22 23 24 25 26 27 28 29 30 31 32

64

63 62 61 60

59 58 57 56 55 54 53 52 51 50 49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

C X _SD IN 1

SAI

_

SC

L

K

S

A

I_

L

RCK

VD

D G N D

VLC

SC L/C C LK

SD A/C DO U T

AD 1/C D IN

AD 0/C S

IN T

R ST

AIN R-

AIN R +

AIN L+

AIN L-

VQ

FI

LT

+

RE

F

G

ND

NC

NC

NC

NC

VA

AG

ND

AO

U

T

B3

-

AO

U

T

B3

+

AO

U

T

A3

+

AO

U

T

A3

-

AO

UT

B2

-

AO

U

T

B2

+

AO

U

T

A2

+

AO U TA2-

AO UT B1-

AO U T B1+

AO U T A1+

AO U TA1-

M U T EC

AG ND

VAR X

RX P7/G PO 7

RX P6/G PO 6

RX P5/G PO 5

RX P4/G PO 4

RX P3/G PO 3

RX P2/G PO 2

RX P1/G PO 1

LPFLT

RXP

0

TXP

VD

DGND

VL

S

S

A

I_

S

DO

UT

RM

CK

CX_

S

DO

UT

A

DCI

N2

A

DCI

N1

OM

CK

CX _LR C K

C X _SC LK

TES

T

CX_

S

DI

N3

CX_

S

DI

N2

20

INT

11

Interrupt (Output) - The CS42516 will generate an interrupt condition as per the Interrupt Mask register. 
See 

“Interrupts” on page 40

 for more details.

RST

12

Reset (Input) - The device enters a low power mode and all internal registers are reset to their default 
settings when low.

AINR-
AINR+

13
14

Differential Right Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma 
modulators via the AINR+/- pins.

AINL+
AINL-

15
16

Differential Left Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma 
modulators via the AINL+/- pins.

VQ

17

Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage.

FILT+

18

Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.

REFGND

19

Reference Ground (Input) - Ground reference for the internal sampling circuits.

NC

20
21
22
23

No Connect Pins - Do not make any connection to these pins.

AOUTA1 +,-
AOUTB1 +,-
AOUTA2 +,-
AOUTB2 +,-
AOUTA3 +,-
AOUTB3 +,-

36,37
35,34
32,33
31,30
28,29
27,26

Differential Analog Output (Output) - The full-scale differential analog output level is specified in the 
Analog Characteristics specification table.

VA
VARX

24
41

Analog Power (Input) - Positive power supply for the analog section. 

AGND

25
40

Analog Ground (Input) - Ground reference. Should be connected to analog ground.

MUTEC

38

Mute Control (Output) - The Mute Control pin outputs high impedance following an initial power-on con-
dition or whenever the PDN bit is set to a ‘1’, forcing the codec into power-down mode. The signal will 
remain in a high impedance state as long as the part is in power-down mode. The Mute Control pin goes 
to the selected “active” state during reset, muting, or if the master clock to left/right clock frequency ratio 
is incorrect. This pin is intended to be used as a control for external mute circuits to prevent the clicks 
and pops that can occur in any single supply system. The use of external mute circuits are not manda-
tory but may be desired for designs requiring the absolute minimum in extraneous clicks and pops.

LPFLT

39

PLL Loop Filter (Output) - An RC network should be connected between this pin and ground.

RXP7/GPO7
RXP6/GPO6
RXP5/GPO5
RXP4/GPO4
RXP3/GPO3
RXP2/GPO2
RXP1/GPO1

42
43
44
45
46
47
48

S/PDIF Receiver Input/ General Purpose Output (Input/Output) - Receiver inputs for S/PDIF encoded 
data. The CS42516 has an internal 8:2 multiplexer to select the active receiver port, according to the 
Receiver Mode Control 2 register. These pins can also be configured as general purpose output pins, 
ADC Overflow indicators or Mute Control outputs according to the RXP/General Purpose Pin Control 
registers.

RXP0

49

S/PDIF Receiver Input (Input) - Dedicated receiver input for S/PDIF encoded data.

TXP

50

S/PDIF Transmitter Output (Output) - S/PDIF encoded data output, mapped directly from one of the 
receiver inputs as indicated by the Receiver Mode Control 2 register.

VLS

53

Serial Port Interface Power (Input) - Determines the required signal level for the serial port interfaces.

SAI_SDOUT

54

Serial Audio Interface Serial Data Output (Output) - Output for two’s complement serial audio PCM 
data from the S/PDIF incoming stream. This pin can also be configured to transmit the output of the inter-
nal and external ADCs.

RMCK

55

Recovered Master Clock (Output) - Recovered master clock output from the External Clock Reference 
(OMCK, pin 59) or the PLL which is locked to the incoming S/PDIF stream or CX_LRCK. 

CX_SDOUT

56

CODEC Serial Data Output (Output) - Output for two’s complement serial audio data from the internal 
and external ADCs.

21

ADCIN1
ADCIN2

58
57

External ADC Serial Input (Input) - The CS42516 provides for up to two external stereo analog to digital 
converter inputs to provide a maximum of six channels on one serial data output line when the CS42516 
is placed in One-Line Mode.

OMCK

59

External Reference Clock (Input) - External clock reference that must be within the ranges specified in 
the register 

“OMCK Frequency (OMCK Freqx)” on page 53

.

TEST

62

Test Pin (Input) - This pin must be connected to DGND.

SAI_LRCK

60

Serial Audio Interface Left/Right Clock (Input/Output) - Determines which channel, Left or Right, is 
currently active on the serial audio data line.

SAI_SCLK

61

Serial Audio Interface Serial Clock (Input/Output) - Serial clock for the Serial Audio Interface.

22