DOWNLOAD Harman Kardon FL 8550 (serv.man13) Service Manual ↓ Size: 3.03 MB | Pages: 87 in PDF or view online for FREE

• Built-in brake function.
• Built-in element to absorb a surge current derived from 

changing motor direction and braking motor drive.

• External motor speed control pin
• Motor direction change circuit.
• Interfaces with CMOS devices.

The KA8301 is a monolithic integrated circuit designed for 
driving bi-directional DC motor with braking and speed con-
trol, and it is suitable for the loading motor driver of VCR 
systems. The speed control can be achieved by adjusting the 
external voltage of the speed control pin.

• Video cassette recorder (VCR) loading motor
• Low current DC motor such audio or video equipment
• General DC motor

KA8301-L

10-SIPH-B

−

25

°

C ~ +75

°

C

 

FL8550

37

1

GND

-

Ground

2

V

OUT1

O

Output 1

3

V

Z1

-

Phase compensation

4

V

R

I

Motor speed control

5

F

IN

I

Input 1

6

R

IN

I

Input 2

7

V

CC1

-

Supply voltage (Signal)

8

V

CC2

I

Supply voltage (Power)

9

V

Z2

I

Phase compensation

10

V

OUT2

O

Output 2

1

2

3

4

5

6

7

8

9

10

GND

V

OUT1

V

Z1

V

R

F

IN

R

IN

V

CC1

V

OUT2

V

CC2

V

Z2

FL8550

38

1

®

●

●

●

●

●

●

±

●

●

●

The PCM1702 is a precision 20-bit digital-to-analog
converter with ultra-low distortion (–96dB typ with a
full scale output). Incorporated into the PCM1702 is
an advanced sign magnitude architecture that elimi-
nates unwanted glitches and other nonlinearities around
bipolar zero. The PCM1702 also features a very low
noise (120dB typ SNR: A-weighted method) and fast
settling current output (200ns typ, 1.2mA step) which
is capable of 16

X

 oversampling rates.

Applications include very low distortion frequency
synthesis and high-end consumer and professional
digital audio applications.

Reference

and

Servo

I

OUT

DCOM

LE

Data

Clock

BPO DC

Bipolar Offset

Balanced Current

Segment DAC A

Input Shift Register

and Control Logic

Balanced Current

Segment DAC B

SERV DC

RF DC

ACOM

+V

CC

–V

CC

© 1993 Burr-Brown Corporation

PDS-1175B

Printed in U.S.A. June, 1995

®

39

FL8550

®

All specifications at 25

°

C, 

±

V

CC

 and +V

DD 

= 

±

5V unless otherwise noted.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.

20

Bits

110

dB

DIGITAL INPUT
Logic Family

TTL/CMOS Compatible

Logic Level:

V

IH

+2.4

+V

DD

V

V

IL

0

0.8

V

I

IH

V

IH

 = +V

DD

±

10

µ

A

I

IL

V

IL

 = 0V

±

10

µ

A

Data Format

Serial, MSB First, BTC

(1)

Input Clock Frequency

12.5

20.0

MHz

(2)

P/U

V

O

 = 0dB

f

S

 = 352.8kHz

(3)

, f = 1002Hz

(4)

–92

–88

dB

V

O

 = –20dB

f

S

 = 352.8kHz

(3)

, f = 1002Hz

(4)

–82

–74

dB

V

O

 = –60dB

f

S

 = 352.8kHz

(3)

, f = 1002Hz

(4)

–46

–40

dB

P/U, -J

V

O

 = 0dB

f

S

 = 352.8kHz

(3)

, f = 1002Hz

(4)

–96

–92

dB

V

O

 = –20dB

f

S

 = 352.8kHz

(3)

, f = 1002Hz

(4)

–83

–76

dB

V

O

 = –60dB

f

S

 = 352.8kHz

(3)

, f = 1002Hz

(4)

–48

–42

dB

P/U, -K

V

O

 = 0dB

f

S

 = 352.8kHz

(3)

, f = 1002Hz

(4)

–100

–96

dB

V

O

 = –20dB

f

S

 = 352.8kHz

(3)

, f = 1002Hz

(4)

–84

–80

dB

V

O

 = –60dB

f

S

 = 352.8kHz

(3)

, f = 1002Hz

(4)

–50

–44

dB

ACCURACY
Level Linearity

At –90dB Signal Level

±

0.5

dB

Gain Error

±

0.5

±

3

%

Bipolar Zero Error

(5)

±

0.25

%

Gain Drift

0

°

C to 70

°

C

±

25

ppm of FSR/

°

C

Bipolar Zero Drift

0

°

C to 70

°

C

±

5

ppm of FSR/

°

C

Warm-up Time

1

minute

Bipolar Zero, A-weighted Filter

110

120

dB

ANALOG OUTPUT
Output Range

±

1.2

mA

Output Impedance

1.0

k

Ω

Settling Time

(

±

0.003% of FSR, 1.2mA Step)

200

ns

Glitch Energy

No Glitch Around Zero

POWER SUPPLY REQUIREMENTS
Supply Voltage Range: +V

CC

 = +V

DD

+4.75

+5.00

+5.25

V

–V

CC

 = –V

DD

–4.75

–5.00

–5.25

V

Combined Supply Current: +I

CC

+V

CC

 = +V

DD

 = +5V

+5.00

+9.0

mA

Combined Supply Current: –I

CC

–V

CC 

= –V

DD 

= –5V

–25.00

–41.0

mA

Power Dissipation

±

V

CC

 = 

±

V

DD

 = 

±

5V

150

250

mW

TEMPERATURE RANGE
Operating

–25

+85

°

C

Storage

–55

+125

°

C

NOTES:  (1) Binary Two’s Complement coding. (2) Ratio of (Distortion

RMS

 + Noise

RMS

) / Signal

RMS

.  (3) D/A converter sample frequency (8 x 44.1kHz; 8

x 

oversampling).

(4) D/A converter output frequency (signal level). (5) Offset error at bipolar zero. (6) Measured using an OPA627 and 5k

Ω

 feedback and an A-weighted filter.

40

FL8550