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SUMMARY DESCRIPTION
The M29W160E is a 16 Mbit (2Mb x8 or 1Mb x16)
non-volatile memory that can be read, erased and
reprogrammed. These operations can be per-
formed using a single low voltage (2.7 to 3.6V)
supply. On power-up the memory defaults to its
Read mode where it can be read in the same way
as a ROM or EPROM.

The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are writ-
ten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents.
The end of a program or erase operation can be
detected and any error conditions identified. The

command set required to control the memory is
consistent with JEDEC standards.
The blocks in the memory are asymmetrically ar-
ranged, see Figures 5 and 6, Block Addresses.
The first or last 64 KBytes have been divided into
four additional blocks. The 16 KByte Boot Block
can be used for small initialization code to start the
microprocessor, the two 8 KByte Parameter
Blocks can be used for parameter storage and the
remaining 32K is a small Main Block where the ap-
plication may be stored.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered TSOP48 (12 x 20mm) and
TFBGA48 (0.8mm pitch) packages. The memory
is supplied with all the bits erased (set to ’1’).

AI06849B

20

A0-A19

W

DQ0-DQ14

VCC

M29W160ET

M29W160EB

E

VSS

15

G

RP

DQ15A–1

RB

BYTE

A0-A19

Address Inputs

DQ0-DQ7

Data Inputs/Outputs

DQ8-DQ14

Data Inputs/Outputs

DQ15A–1

Data Input/Output or Address Input

E

Chip Enable

G

Output Enable

W

Write Enable

RP

Reset/Block Temporary Unprotect

RB

Ready/Busy Output

BYTE

Byte/Word Organization Select

V

CC

Supply Voltage

V

SS

Ground

NC

Not Connected Internally

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Service manual DVD37EU

Page 97 of 117

DQ3

DQ9

DQ2

A6

DQ0

W

A3

RB

DQ6

A8

A9

DQ13

A17

A10

DQ14

A2

DQ12

DQ10

DQ15A–1

VCC

DQ4

DQ5

A7

DQ7

NC

NC

AI06850

M29W160ET

M29W160EB

12

1

13

24

25

36

37

48

DQ8

NC

A19

A1

A18

A4

A5

DQ1

DQ11

G

A12

A13

A16

A11

BYTE

A15

A14

VSS

E

A0

RP

VSS

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Service manual DVD37EU

Page 98 of 117

Rev. 3

3V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM,

10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE

■

– 8 to 32K dual voltage High Density Flash (HD-

Flash) or ROM with read-out protection capa-

bility. In-Application Programming and In-

Circuit Programming for HDFlash devices

– 384 to 1K bytes RAM
– HDFlash endurance: 100 cycles, data reten-

tion: 20 years at 55°C

■

– Clock sources: crystal/ceramic resonator os-

cillators, internal RC oscillator, and bypass for

external clock

– PLL for 2x frequency multiplication
– Four Power Saving Modes: Halt, Active-Halt,

Wait and Slow

■

– Nested interrupt controller
– 10 interrupt vectors plus TRAP and RESET
– 9/6 external interrupt lines (on 4 vectors)

■

– 32/24 multifunctional bidirectional I/O lines
– 22/17 alternate function lines
– 12/10 high sink outputs

■

– Main Clock Controller with: Real time base,

Beep and Clock-out capabilities

– Configurable watchdog timer
– 16-bit Timer A with: 1 input capture, 1 output

compare, external clock input, PWM and

pulse generator modes

– 16-bit Timer B with: 2 input captures, 2 output

compares, PWM and pulse generator modes

■

– SPI synchronous serial interface
– SCI asynchronous serial interface 

■

– 10-bit ADC with up to 12 input ports

■

– 8-bit Data Manipulation
– 63 Basic Instructions
– 17 main Addressing Modes
– 8 x 8 Unsigned Multiply Instruction

■

– Full hardware/software development package
– In-Circuit Testing capability

Program memory - 
bytes

Flash 32K

Flash 16K

Flash 8K

ROM 16K

ROM 8K

RAM (stack) - bytes

1024 (256)

512 (256)

384 (256)

512 (256)

384 (256)

Voltage Range 

2.85 to 3.6V

Temp. Range 

up to -40°C to +85°C

Packages

TQFP44 10x10, SDIP32, TQFP32 7x7

1

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Service manual DVD37EU

Page 99 of 117

The ST72F324L and ST72324BL devices are
members of the ST7 microcontroller family de-
signed for the 3V operating range. They can be
grouped as follows:

– The 32-pin devices are designed for mid-range 

applications

– The 44-pin devices target the same range of ap-

plications requiring more than 24 I/O ports.

All devices are based on a common industry-
standard 8-bit core, featuring an enhanced instruc-

tion set and are available with FLASH or ROM pro-
gram memory. 

Under software control, all devices can be placed
in WAIT, SLOW, ACTIVE-HALT or HALT mode,
reducing power consumption when the application
is in idle or stand-by state. 

The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.

8-BIT CORE

ALU

ADDR

ESS

 A

ND DAT

A

 BUS

OSC1

V

PP

CONTROL

PROGRAM

(8K - 60K Bytes)

V

DD

RESET

PORT F

PF7:6,4,2:0

TIMER A

BEEP

PORT A

RAM

(384 - 2048 Bytes)

PORT C

10-BIT ADC

V

AREF

V

SSA

PORT B

PB4:0

PORT E

PE1:0

(2 bits)

SCI

TIMER B

PA7:3

(5 bits on J devices)

PORT D

PD5:0

SPI

PC7:0

(8 bits)

V

SS

WATCHDOG

OSC

OSC2

MEMORY

MCC/RTC/BEEP

(4 bits on K devices)

(5 bits on J devices)
(3 bits on K devices)

(6 bits on J devices)
(2 bits on K devices)

(6 bits on J devices)
(5 bits on K devices)

3

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Service manual DVD37EU

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