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 CLK 

 System Clock 

 Active on the positive going edge to sample all inputs 

  CS  

 Chip Select 

  Disables or enables device operation by masking or enabling all 
  inputs except CLK , CKE and L(U)DQM 

 CKE 

 Clock Enable 

  Masks system clock to freeze operation from the next clock cycle. 
  CKE should be enabled at least one cycle prior new command. 
  Disable input buffers for power down in standby. 

 A0 ~ A11 

 Address 

  Row / column address are multiplexed on the same pins. 
  Row address : RA0~RA11, column address : CA0~CA7 

  A12 , A13 

  Bank Select Address 

  Selects bank to be activated during row address latch time. 
  Selects bank for read / write during column address latch time. 

  RAS  

 Row Address Strobe 

  Latches row addresses on the positive going edge of the CLK with 
  RAS  low. 
  Enables row access & precharge. 

  CAS  

 Column Address Strobe 

  Latches column address on the positive going edge of the CLK with
  CAS  low. 
  Enables column access. 

  WE  

 Write Enable 

  Enables write operation and row precharge. 

  Latches data in starting from  CAS ,  WE  active. 

  L(U)DQM 

  Data Input / Output Mask 

  Makes data output Hi-Z, t

SHZ

 after the clock and masks the output. 

  Blocks data input when L(U)DQM active. 

  DQ0 ~ DQ15 

  Data Input / Output 

  Data inputs / outputs are multiplexed on the same pins. 

  VDD / VSS 

  Power Supply / Ground 

  Power and ground for the input buffers and the core logic. 

  VDDQ / VSSQ    Data Output Power / Ground 

  Isolated power supply and ground for the output buffers to provide 
  improved noise immunity.   

  NC 

  No Connection 

  This pin is recommended to be left No Connection on the device. 

L(U)DQM

DQ

 Mode 
 Register

 

Control Logic 

 Column
 Address
 Buffer
      & 
 Refresh
 Counter

Row 
Address
Buffer 
    & 
Refresh
Counter

Bank D

Row Decode

r

 

Bank A

Bank B

Bank C

Sense Amplifier

Column Decoder 

Data Control Circuit

Latch Circuit

 

Input & Out

put 

Buf

fer 

Address 

 Clock 
 Generator

 

CLK 

CKE 

Command Deco

der

 

CS 

RAS 

CAS 

WE 

harman/kardon

DVD 29/230 Service Manual

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DQ3

DQ9

DQ2

A6

DQ0

W

A3

RB

DQ6

A8

A9

DQ13

A17

A10

DQ14

A2

DQ12

DQ10

DQ15A–1

VCC

DQ4

DQ5

A7

DQ7

NC

NC

AI06850

M29W160ET

M29W160EB

12

1

13

24

25

36

37

48

DQ8

NC

A19

A1

A18

A4

A5

DQ1

DQ11

G

A12

A13

A16

A11

BYTE

A15

A14

VSS

E

A0

RP

VSS

harman/kardon

DVD 29/230 Service Manual

Page 42 of 55

7/40

AI02985B

6

5

4

3

2

1

VSS

DQ15

A–1

A15

A14

A12

A13

DQ3

DQ11

DQ10

A18

NC

RB

DQ1

DQ9

DQ8

DQ0

A6

A17

A7

G

E

A0

A4

A3

DQ2

DQ6

DQ13

DQ14

A10

A8

A9

DQ4

VCC

DQ12

DQ5

A19

NC

RP

W

A11

DQ7

A1

A2

VSS

A5

NC

A16

BYTE

G

F

E

B

A

D

C

H

harman/kardon

DVD 29/230 Service Manual

Page 43 of 55

  The PC-17L1 has one channel in a 4-pin DIP package.
  The PC-17L2 has two channels in a 8-pin DIP package.
  The PC-17L4 has four channels in a 16-pin DIP package.

  • Small Package Size

 

  • Collector-Emitter Voltage : Min.35V
  • Current Transfer Ratio : Min.50% (at I

F

=5mA, V

CE

=5V)

  • Electrical Isolation Voltage : AC5000V

rms

  • UL Recognized File No. E107486

  • Interface between two circuits of different potential

  • Programmable Logic Control
  • Power Supply
  • Computer Terminals

These Photocouplers consist of a Gallium Arsenide Infrared Emitting
Diode and a Silicon NPN Phototransistor per a channel.

  • Creepage/Clearance between Input and Output : Min. 7.0mm

  • Vending Machine, Cordless Phone, Key Phone, Fax, Motor Control

6.5

0.25

0.51Min.

3.5

0.25

2.5Min.

2.54 0.25

1.2

9.7 0.25

1

4

3

2

7

5

6

8

Orientation Mark

6.5

0.25

Orientation Mark

0.51Min.

3.5

0.25

2.5Min.

0.5

1.2

2.54 0.25

4.6 0.25

3

4

2

1

6.5

0.25

19.8± 0.25

3.5

0.25

0.51Min.

2.5Min.

0.5

1.2

2.54 0.25

8

7

5

6

2

3

4

10

12

16

14

9

11

13

15

1

Orientation Mark

6.5

7.62 0.25

10.16 0.25

0.25

(Unit : mm)

harman/kardon

DVD 29/230 Service Manual

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