Harman Kardon DMC 250 (serv.man2) Service Manual ▷ View online
HY57V161610E
Rev. 0.2 / Aug. 2003 2
PIN CONFIGURATION
V
SS
DQ15
DQ14
VSSQ
DQ13
DQ13
DQ12
VDDQ
DQ11
DQ11
DQ10
VSSQ
DQ9
DQ9
DQ8
VDDQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
DD
DQ0
DQ1
V
SSQ
DQ2
DQ3
V
DDQ
DQ4
DQ5
V
SSQ
DQ6
VDDQ
/WE
/CAS
/RAS
/RAS
/CS
A11
A10
A10
A0
A1
A2
A3
A1
A2
A3
V
DD
50pin TSOP II
400mil x 825mil
0.8mm pin pitch
27
26
26
DQ7
LDQM
V
SS
DQ15
DQ14
VSSQ
DQ13
DQ13
DQ12
VDDQ
DQ11
DQ11
DQ10
VSSQ
DQ9
DQ9
DQ8
VDDQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
DD
DQ0
DQ1
V
SSQ
DQ2
DQ3
V
DDQ
DQ4
DQ5
V
SSQ
DQ6
VDDQ
/WE
/CAS
/RAS
/RAS
/CS
A11
A10
A10
A0
A1
A2
A3
A1
A2
A3
V
DD
50pin TSOP II
400mil x 825mil
0.8mm pin pitch
27
26
26
DQ7
LDQM
PIN DESCRIPTION
PIN
PIN NAME
DESCRIPTION
CLK
Clock
The system clock input. All other inputs are referenced to the SDRAM on the rising
edge of CLK.
edge of CLK.
CKE
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will be one of the
states among power down, suspend or self refresh.
states among power down, suspend or self refresh.
CS
Chip Select
Command input enable or mask except CLK, CKE and DQM
BA
Bank Address
Select either one of banks during both RAS and CAS activity.
A0 ~ A10
Address
Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
Auto-precharge flag : A10
RAS, CAS, WE
Row Address Strobe,
Column Address Strobe, Write
Enable
Column Address Strobe, Write
Enable
RAS, CAS and WE define the operation.
Refer function truth table for details
Refer function truth table for details
LDQM, UDQM
Data Input/Output Mask
DQM control output buffer in read mode and mask input data in write mode
DQ0 ~ DQ15
Data Input/Output
Multiplexed data input / output pin
V
DD
/V
SS
Power Supply/Ground
Power supply for internal circuit and input buffer
V
DDQ
/V
SSQ
Data Output Power/Ground
Power supply for DQ
NC
No Connection
No connection
harman/kardon
DMC250/230 Service Manual
Page 37 of 110
ADV7320/ADV7321
Rev. 0 | Page 17 of 88
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64
GND_
IO
63
CLKIN_
B
62
S9
61
S8
60
S7
59
S6
58
S5
57
DGND
56
V
DD
55
S4
54
S3
53
S2
52
S1
51
S0
50
S_H
SYN
C
49
S_VSYN
C
47
R
SET1
46
V
REF
45
COMP1
42
DAC C
43
DAC B
44
DAC A
48
S_BLANK
41
V
AA
40
AGND
39
DAC D
37
DAC F
36
COMP2
35
R
SET2
34
EXT_LF
33
RESET
38
DAC E
2
Y0
3
Y1
4
Y2
7
Y5
6
Y4
5
Y3
1
V
DD_IO
8
Y6
9
Y7
10
V
DD
12
Y8
13
Y9
14
C0
15
C1
16
C2
11
DGND
17
C3
18
C4
19
I
2
C
20
ALS
B
21
SD
A
22
SC
LK
23
P_H
SYN
C
24
P_VSYN
C
25
P
_
BLANK
26
C5
27
C6
28
C7
29
C8
30
C9
31
RTC_
S
CR_
TR
32
CLKIN_
A
PIN 1
ADV7320/ADV7321
TOP VIEW
(Not to Scale)
05067-019
Figure 19. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Input/Output Description
11, 57
DGND
G
Digital Ground.
40
AGND
G
Analog Ground.
32
CLKIN_A
I
Pixel Clock Input for HD (74.25 MHz Only, PS Only (27 MHz), SD Only (27 MHz).
63
CLKIN_B
I
Pixel Clock Input. Requires a 27 MHz reference clock for progressive scan mode or a 74.25 MHz
(74.1758 MHz) reference clock in HDTV mode. This clock is only used in dual modes.
(74.1758 MHz) reference clock in HDTV mode. This clock is only used in dual modes.
45, 36
COMP1,
COMP2
COMP2
O
Compensation Pin for DACs. Connect 0.1 µF capacitor from COMP pin to V
AA
.
44
DAC A
O
CVBS/Green/Y/Y Analog Output.
43
DAC B
O
Chroma/Blue/U/Pb Analog Output.
42
DAC C
O
Luma/Red/V/Pr Analog Output.
39
DAC D
O
In SD Only Mode: CVBS/Green/Y Analog Output; in HD Only Mode and Simultaneous HD/SD
Mode: Y/Green [HD] Analog Output.
Mode: Y/Green [HD] Analog Output.
38
DAC E
O
In SD Only Mode: Luma/Blue/U Analog Output; in HD Only Mode and Simultaneous HD/SD
Mode: Pr/Red Analog Output.
Mode: Pr/Red Analog Output.
37
DAC F
O
In SD Only Mode: Chroma/Red/V Analog Output; in HD Only Mode and Simultaneous HD/SD
Mode: Pb/Blue [HD] Analog Output.
Mode: Pb/Blue [HD] Analog Output.
23
P_HSYNC
I
Video Horizontal Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode.
24
P_VSYNC
I
Video Vertical Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode.
25
P_BLANK
I
Video Blanking Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode.
48
S_BLANK
I/O
Video Blanking Control Signal for SD Only.
49
S_VSYNC
I/O
Video Vertical Sync Control Signal for SD Only.
50
S_HSYNC
I/O
Video Horizontal Sync Control Signal for SD Only.
13,12,
9–2
9–2
Y9 to Y0
I
SD or Progressive Scan/HDTV Input Port for Y Data. Input port for interleaved progressive scan
data. The LSB is set up on Pin Y0. For 8-bit data input, LSB is set up on Y2.
data. The LSB is set up on Pin Y0. For 8-bit data input, LSB is set up on Y2.
30–26,
18–14
18–14
C9 to C0
I
Progressive Scan/HDTV Input Port 4:4:4 Input Mode. This port is used for the Cb[Blue/U] data.
The LSB is set up on Pin C0. For 8-bit data input, LSB is set up on C2.
The LSB is set up on Pin C0. For 8-bit data input, LSB is set up on C2.
harman/kardon
DMC250/230 Service Manual
Page 38 of 110
AM5888S
Motor Driver ICs
A
A
M
M
t
t
e
e
k
k
S
S
E
E
M
M
I
I
C
C
O
O
N
N
D
D
U
U
C
C
T
T
O
O
R
R
S
S
F
F
e
e
b
b
2
2
0
0
0
0
5
5
V
V
1
1
.
.
2
2
- 4 -
Pin configuration
VOSL-
MUTE
VINTK
VCTL
Vcc2
VOLD-
VOLD+
TRB_2
NC
VINLD
VOTK-
VOTK+
VINFC
TRB_1
FWD
VOSL+
VOFC+
VOFC-
GND
NC
BIAS
15
16
17
18
19
20
21
REGO 2
VINSL+
REGO 1
REV
Vcc1
VOTR-
VOTR+
22
23
24
25
26
27
14
12
11
10
9
7
6
5
4
3
2
1
8
13
28
AM5888S
harman/kardon
DMC250/230 Service Manual
Page 39 of 110
1
Features
•
Medium-voltage and Standard-voltage Operation
– 5.0 (V
CC
= 4.5V to 5.5V)
– 2.7 (V
CC
= 2.7V to 5.5V)
•
Automotive Temperature Range –40
°
C to 125
°
C
•
Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),
1024 x 8 (8K) or 2048 x 8 (16K)
1024 x 8 (8K) or 2048 x 8 (16K)
•
Two-wire Serial Interface
•
Schmitt Trigger, Filtered Inputs for Noise Suppression
•
Bidirectional Data Transfer Protocol
•
400 kHz (2.7V) Compatibility
•
Write Protect Pin for Hardware Data Protection
•
8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes
•
Partial Page Writes are Allowed
•
Self-timed Write Cycle (5 ms max)
•
High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
– Data Retention: 100 Years
•
8-lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP Packages
Description
The AT24C01A/02/04/08A/16A provides 1024/2048/4096/8192/16384 bits of serial
electrically erasable and programmable read-only memory (EEPROM) organized as
128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many
automotive applications where low-power and low-voltage operation are essential.
The AT24C01A/02/04/08A/16A is available in space-saving 8-lead PDIP, 8-lead
JEDEC SOIC, and 8-lead TSSOP packages and is accessed via a two-wire serial
interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V) versions.
electrically erasable and programmable read-only memory (EEPROM) organized as
128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many
automotive applications where low-power and low-voltage operation are essential.
The AT24C01A/02/04/08A/16A is available in space-saving 8-lead PDIP, 8-lead
JEDEC SOIC, and 8-lead TSSOP packages and is accessed via a two-wire serial
interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V) versions.
Table 1. Pin Configurations
Pin Name
Function
A0
−
A2
Address Inputs
SDA
Serial Data
SCL
Serial Clock Input
WP
Write Protect
NC
No Connect
Two-wire
Automotive
Temperature
Serial EEPROM
Automotive
Temperature
Serial EEPROM
1K (128 x 8)
2K (256 x 8)
4K (512 x 8)
8K (1024 x 8)
16K (2048 x 8)
AT24C01A
AT24C02
AT24C04
AT24C08A
AT24C16A
AT24C02
AT24C04
AT24C08A
AT24C16A
5092B–SEEPR–9/05
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
S
CL
S
DA
8
-le
a
d PDIP
8
-le
a
d
S
OIC
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
S
CL
S
DA
8
-le
a
d T
SS
OP
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
S
CL
S
DA
harman/kardon
DMC250/230 Service Manual
Page 40 of 110
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