Harman Kardon AVR 365 Service Manual ▷ View online
ADV3014
ADI Confidential
Rev. Sp0 | Page 8 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADV3014
TOP VIEW
(Not to Scale)
PIN 1
0
90
68
-0
02
1
DDCC_SCL
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
73
DVDDIO
74
TEST5
75
TEST6
76
TEST7
77
TEST8
78
SDATA
79
SCL
80
DGND
81
DVDD
82
INT1
83
INT2
84
INT_TX
85
DGNDIO
86
DVDDIO
87
TEST9
88
TEST10
89
TEST11
90
TEST12
91
TEST13
92
DGND
93
DVDD
94
TEST14
95
TEST15
96
TEST16
97
RESET
98
PWRDN
99
PGND
100
PVDD
101
XTAL
102
XTAL1
103
PVDD
104
PGND
105
HP_CTRLA
106
5V_DETA
107
RTERM
108
DDCA_SDA
109
11
0
111
11
2
11
3
11
4
11
5
11
6
11
7
11
8
11
9
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
DDC
C_S
D
A
37
TX
P
L
V
D
D
38
TX
P
G
N
D
39
TX
P
L
GN
D
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
EX
T
_
SW
IN
G
HP
_T
X
TE
S
T0
T
XD
D
C
_
SD
A
T
X
DD
C_S
C
L
T
X
AV
DD
TX
GN
D
TX
C
–
TX
C
+
TX
GN
D
TX
0
–
TX
0
+
TX
GN
D
TX
1
–
TX
1
+
T
X
AV
DD
TX
2
–
TX
2
+
TX
GN
D
CE
C
DG
ND
DV
DD
AL
S
B
CS
EP
_
S
C
K
EP
_
C
S
EP
_
M
O
SI
EP
_
M
ISO
TE
S
T1
TE
S
T2
TE
S
T3
TE
S
T4
DG
ND
IO
5V
_DE
T
C
HP
_CT
R
L
C
RX
B_2+
RX
B_2–
TV
D
D
RX
B_1+
RX
B_1–
CG
ND
RX
B_0+
RX
B_0–
TV
D
D
RX
B_C+
RX
B_C–
CG
ND
CV
DD
DDCB_S
C
L
DDCB_S
D
A
DV
DD
DG
ND
5V
_DE
T
B
HP
_CT
R
L
B
RX
A_2+
RX
A_2–
TV
D
D
RX
A_1+
RX
A_1–
CG
ND
RX
A_0+
RX
A_0–
TV
D
D
RX
A_C+
RX
A_C–
CG
ND
CV
DD
DDCA_S
C
L
CVDD
CGND
RXC_C–
RXC_C+
RXC_C+
TVDD
RXC_0–
RXC_0+
RXC_0+
CGND
RXC_1–
RXC_1+
RXC_1+
TVDD
RXC_2–
RXC_2+
RXC_2+
HP_CTRLD
5V_DETD
DGND
DVDD
DDCD_SDA
DDCD_SCL
CVDD
CGND
RXD_C–
RXD_C+
RXD_C+
TVDD
RXD_0–
RXD_0+
RXD_0+
CGND
RXD_1–
RXD_1+
RXD_1+
TVDD
RXD_2–
RXD_2+
RXD_2+
CVDD
CGND
TXPVDD
Figure 4. Pin Configuration
Table 5: Pin Function Descriptions
Pin No.
Mnemonic
Type
Description
1
DDCC_SCL
Digital input
HDCP Slave Serial Clock Port C. DDCC_SCL is a 3.3 V input that is 5 V tolerant.
2
CVDD
Power
Receiver Comparator Supply Voltage (1.8 V).
3
CGND
Ground
TVDD and CVDD Ground.
4
RXC_C−
HDMI input
Digital Input Clock Complement of Port C in the HDMI Interface.
5
RXC_C+
HDMI input
Digital Input Clock True of Port C in the HDMI Interface.
6
TVDD
Power
Receiver Terminator Supply Voltage (3.3 V).
7
RXC_0−
HDMI input
Digital Input Channel 0 Complement of Port C in the HDMI Interface.
8
RXC_0+
HDMI input
Digital Input Channel 0 True of Port C in the HDMI Interface.
9
CGND
Ground
TVDD and CVDD Ground.
10
RXC_1−
HDMI input
Digital Input Channel 1 Complement of Port C in the HDMI Interface.
11
RXC_1+
HDMI input
Digital Input Channel 1 True of Port C in the HDMI Interface.
12
TVDD
Power
Receiver Terminator Supply Voltage (3.3 V).
13
RXC_2−
HDMI input
Digital Input Channel 2 Complement of Port C in the HDMI Interface.
Anam Electronics
June 30, 2010
ADI Confidential
Harman Kardon
AVR 365/230V Service Manual
Page 109 of 176
Page 2 / 39
Revision 1.3
Apr., 2010
256M Double Data Rate Synchronous DRAM
A3S56D30FTP
A3S56D40FTP
A3S56D40FTP
CLK, /CLK
: Master Clock
CKE
: Clock Enable
/CS
: Chip Select
/RAS
: Row Address Strobe
/CAS
: Column Address Strobe
/WE
: Write Enable
A0-12
: Address Input
BA0,1
: Bank Address Input
Vdd
: Power Supply
VddQ
: Power Supply for Output
Vss
: Ground
VssQ
: Ground for Output
DQ0-15
: Data I/O (x16)
UDM, LDM
: Write Mask (x16)
Pin Assignment (Top View) 66-pin TSOP
DM
: Write Mask (x8)
DQ0-7
: Data I/O (x8)
UDQS, LDQS
: Data Strobe (x16)
DQS
: Data Strobe (x8)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
Vdd
DQ0
DQ0
VddQ
DQ1
DQ2
DQ2
VssQ
DQ3
DQ4
DQ4
VddQ
DQ5
DQ6
DQ6
VssQ
DQ7
NC
VddQ
LDQS
NC
Vdd
NC
LDM
/WE
/CAS
/RAS
/RAS
/CS
NC
BA0
BA1
BA1
A10/AP
A0
A1
A2
A3
A1
A2
A3
Vdd
Vss
DQ15
VssQ
DQ14
DQ13
VddQ
DQ12
DQ11
VssQ
DQ10
DQ9
VddQ
DQ8
NC
VssQ
UDQS
NC
VREF
Vss
UDM
DQ15
VssQ
DQ14
DQ13
VddQ
DQ12
DQ11
VssQ
DQ10
DQ9
VddQ
DQ8
NC
VssQ
UDQS
NC
VREF
Vss
UDM
/CLK
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
Vss
66pin TSOP(II)
400mil width
x
875mil length
0.65mm
Lead Pitch
Row
A0-12
Column
A0-9 (x8)
A0-8 (x16)
Vdd
DQ0
DQ0
VddQ
NC
DQ1
VssQ
NC
DQ2
VddQ
NC
DQ3
VssQ
NC
NC
NC
VddQ
NC
NC
NC
Vdd
NC
NC
NC
/WE
/CAS
/RAS
/RAS
/CS
NC
BA0
BA1
BA1
A10/AP
A0
A1
A2
A3
A1
A2
A3
Vdd
Vss
DQ7
VssQ
NC
DQ6
VddQ
NC
DQ5
VssQ
NC
DQ4
VddQ
NC
NC
VssQ
DQS
NC
VREF
Vss
DM
DQ7
VssQ
NC
DQ6
VddQ
NC
DQ5
VssQ
NC
DQ4
VddQ
NC
NC
VssQ
DQS
NC
VREF
Vss
DM
/CLK
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
Vss
x8
x16
VREF
: SSTL_2 reference voltage
Harman Kardon
AVR 365/230V Service Manual
Page 110 of 176
Harman Kardon
AVR 365/230V Service Manual
Page 111 of 176
1
IDT74FCT38072
3.3V CMOS 1-TO-2 CLOCK DRIVER
3.3V CMOS 1-TO-2 CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
AUGUST 2004
2004 Integrated Device Technology, Inc.
DSC-6595/5
c
IDT74FCT38072
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS
1-TO-2 CLOCK DRIVER
1-TO-2 CLOCK DRIVER
DESCRIPTION:
The FCT38072 is a 3.3V clock driver built using advanced CMOS
technology. This low skew clock driver offers 1:2 fanout. The large fanout from
a single input reduces loading on the preceding driver and provides an efficient
clock distribution network. Multiple power and grounds reduce noise. Typical
applications are clock and signal distribution.
a single input reduces loading on the preceding driver and provides an efficient
clock distribution network. Multiple power and grounds reduce noise. Typical
applications are clock and signal distribution.
FUNCTIONAL BLOCK DIAGRAM
IN
O
1
O
2
PIN CONFIGURATION
V
CC
GND
GND
GND
V
CC
IN
O
2
O
1
1
2
3
4
5
6
7
8
SOIC
TOP VIEW
FEATURES:
• Advanced CMOS Technology
• Guaranteed low skew < 100ps (max.)
• Very low duty cycle distortion< 350ps (max.)
• High speed propagation delay< 3ns (max.)
• Very low CMOS power levels
• TTL compatible inputs and outputs
• 1:2 fanout
• Maximum output rise and fall time < 1ns (max.)
• Low input capacitance: 3pF typical
• V
• Guaranteed low skew < 100ps (max.)
• Very low duty cycle distortion< 350ps (max.)
• High speed propagation delay< 3ns (max.)
• Very low CMOS power levels
• TTL compatible inputs and outputs
• 1:2 fanout
• Maximum output rise and fall time < 1ns (max.)
• Low input capacitance: 3pF typical
• V
CC
= 3.3V ± 0.3V
• Inputs can be driven from 3.3V or 5V components
• Operating frequency up to 166MHz
• Available in SOIC package
• Operating frequency up to 166MHz
• Available in SOIC package
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Harman Kardon
AVR 365/230V Service Manual
Page 112 of 176
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