DOWNLOAD Harman Kardon AVR 235 (serv.man12) Service Manual ↓ Size: 19.7 MB | Pages: 114 in PDF or view online for FREE

Model
AVR 235 (serv.man12)
Pages
114
Size
19.7 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
avr-235-sm12.pdf
Date
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PIN/FUNCTION (Continued)
No.
Pin Name
I/O
Function
31
PDN
I
Power-Down Mode Pin
When “L”, the AK4114 is powered-down and reset.
CM0
I
Master Clock Operation Mode 0 Pin in Parallel Mode
CDTO
O
Control Data Output Pin in Serial Mode, IIC= “L”.
32
CAD1
I
Chip Address 1 Pin in Serial Mode, IIC= “H”.
CM1
I
Master Clock Operation Mode 1 Pin in Parallel Mode
CDTI
I
Control Data Input Pin in Serial Mode, IIC= “L”.
33
SDA
I/O
Control Data Pin in Serial Mode, IIC= “H”.
OCKS1
I
Output Clock Select 1 Pin in Parallel Mode
CCLK
I
Control Data Clock Pin in Serial Mode, IIC= “L”
34
SCL
I
Control Data Clock Pin in Serial Mode, IIC= “H”
OCKS0
I
Output Clock Select 0 Pin in Parallel Mode
CSN
I
Chip Select Pin in Serial Mode, IIC=”L”.
35
CAD0
I
Chip Address 0 Pin in Serial Mode, IIC= “H”.
36
INT0
O
Interrupt 0 Pin
37
INT1
O
Interrupt 1 Pin
38
AVDD
I
Analog Power Supply Pin, 3.3V
39
R
-
External Resistor Pin
18k
Ω
 +/-1% resistor should be connected to AVSS externally.
40
VCOM
-
Common Voltage Output Pin
0.47µF capacitor should be connected to AVSS externally.
41
AVSS
I
Analog Ground Pin
42
RX0
I
Receiver Channel 0 Pin (Internal biased pin)
This channel is default in serial mode.
43
NC(AVSS)
I
No Connect
No internal bonding. This pin should be connected to AVSS.
44
RX1
I
Receiver Channel 1 Pin (Internal biased pin)
45
TEST1
I
TEST 1 pin.
This pin should be connected to AVSS.
46
RX2
I
Receiver Channel 2 Pin (Internal biased pin)
47
NC(AVSS)
I
No Connect
No internal bonding. This pin should be connected to AVSS.
48
RX3
I
Receiver Channel 3 Pin (Internal biased pin)
Note 1. All input pins except internal biased pins should not be left floating.
PIN ASSIGNMENT (74HCU04AFN : IC71,72,76 )
LOGIC SYMBOL
TRUTH TABLE
1
2
3
4
5
6
7
1A
1Y
2A
2Y
3A
3Y
GND
6A
6Y
5A
5Y
4A
4Y
Vcc
14
13
12
11
10
9
8
A
L
H
Y
H
L         
1A
(1)
(3)
(5)
(9)
(11)
(13)
2A
3A
4A
5A
6A
1Y
2Y
3Y
4Y
5Y
6Y
(2)
(4)
(6)
(8)
(10)
(12) 
© 1999 Fairchild Semiconductor Corporation
DS009913
www.fairchildsemi.com
November 1988
Revised November 1999
7
4
AC
0
4
 • 
74ACT04 Hex
 I
n
vert
e
r
74AC04 • 74ACT04
 Hex Inverter
General Description
The AC/ACT04 contains six inverters.
Features
■
I
CC
 reduced by 50% on 74AC only
■
Outputs source/sink 24 mA
■
ACT04 has TTL-compatible inputs
 
Ordering Code: 
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. (PC not available in Tape and Reel.)
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT
 is a trademark of Fairchild Semiconductor Corporation.
Order Number
Package Number
Package Description
74AC04SC M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
74AC04SJ 
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC04MTC 
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC04PC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT04SC 
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
74ACT04MTC 
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT04PC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names
Description
A
n
Inputs
O
n
Outputs
74ACT04SC : IC52,75,83,84
R
×
5VT
2
BLOCK DIAGRAMS
• 
Nch Open Drain Output (R
×
5VT
××
A)
• 
CMOS Output (R
×
5VT
××
C)
TIME CHART
DEFINITION OF OUTPUT DELAY TIME t
PLH
2
3
Vref
OUT
GND
V
DD
–
+
1
V
DD
2
1
3
Vref
OUT
GND
–
+
Detector Threshold Hysteresis
t
PLH
Released Voltage     +V
DET
 
Detected Voltage      –V
DET
 
Supply Voltage
(V
DD
)
Output Voltage
(OUT)
Minimum Operating Voltage
GND
GND
t
PLH
t
PHL
Input Voltage
(V
DD
)
Output Voltage
Nch Open Drain Output 
GND
GND
2.5V
5.0V
0.7V
+V
DET 
+ 2.0V
t
PLH
t
PHL
CMOS Output 
GND
GND
0.7V
+V
DET
 + 2.0V
+V
DET
 +2.0V
+V
DET
 + 2.0V
2
Input Voltage
(V
DD
)
Output Voltage
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